/* * SH-7750 memory-mapped registers * This file based on information provided in the following document: * "Hitachi SuperH (tm) RISC engine. SH7750 Series (SH7750, SH7750S) *  Hardware Manual" *  Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd. * * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia * Author: Alexandra Kossovsky <sasha@oktet.ru> *         Victor V. Vengerov <vvv@oktet.ru> * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at *  http://www.rtems.com/license/LICENSE. * * @(#) sh7750_regs.h,v 1.2.4.1 2003/09/04 18:46:00 joel Exp */#ifndef __SH7750_REGS_H__#define __SH7750_REGS_H__/* * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address)  and * in 0x1f000000 - 0x1fffffff (area 7 address) */#define SH7750_P4_BASE       0xff000000	/* Accessable only in					   priveleged mode */#define SH7750_A7_BASE       0x1f000000	/* Accessable only using TLB */#define SH7750_P4_REG32(ofs) (SH7750_P4_BASE + (ofs))#define SH7750_A7_REG32(ofs) (SH7750_A7_BASE + (ofs))/* * MMU Registers *//* Page Table Entry High register - PTEH */#define SH7750_PTEH_REGOFS    0x000000	/* offset */#define SH7750_PTEH           SH7750_P4_REG32(SH7750_PTEH_REGOFS)#define SH7750_PTEH_A7        SH7750_A7_REG32(SH7750_PTEH_REGOFS)#define SH7750_PTEH_VPN       0xfffffd00	/* Virtual page number */#define SH7750_PTEH_VPN_S     10#define SH7750_PTEH_ASID      0x000000ff	/* Address space identifier */#define SH7750_PTEH_ASID_S    0/* Page Table Entry Low register - PTEL */#define SH7750_PTEL_REGOFS    0x000004	/* offset */#define SH7750_PTEL           SH7750_P4_REG32(SH7750_PTEL_REGOFS)#define SH7750_PTEL_A7        SH7750_A7_REG32(SH7750_PTEL_REGOFS)#define SH7750_PTEL_PPN       0x1ffffc00	/* Physical page number */#define SH7750_PTEL_PPN_S     10#define SH7750_PTEL_V         0x00000100	/* Validity (0-entry is invalid) */#define SH7750_PTEL_SZ1       0x00000080	/* Page size bit 1 */#define SH7750_PTEL_SZ0       0x00000010	/* Page size bit 0 */#define SH7750_PTEL_SZ_1KB    0x00000000	/*   1-kbyte page */#define SH7750_PTEL_SZ_4KB    0x00000010	/*   4-kbyte page */#define SH7750_PTEL_SZ_64KB   0x00000080	/*   64-kbyte page */#define SH7750_PTEL_SZ_1MB    0x00000090	/*   1-Mbyte page */#define SH7750_PTEL_PR        0x00000060	/* Protection Key Data */#define SH7750_PTEL_PR_ROPO   0x00000000	/*   read-only in priv mode */#define SH7750_PTEL_PR_RWPO   0x00000020	/*   read-write in priv mode */#define SH7750_PTEL_PR_ROPU   0x00000040	/*   read-only in priv or user mode */#define SH7750_PTEL_PR_RWPU   0x00000060	/*   read-write in priv or user mode */#define SH7750_PTEL_C         0x00000008	/* Cacheability						   (0 - page not cacheable) */#define SH7750_PTEL_D         0x00000004	/* Dirty bit (1 - write has been						   performed to a page) */#define SH7750_PTEL_SH        0x00000002	/* Share Status bit (1 - page are						   shared by processes) */#define SH7750_PTEL_WT        0x00000001	/* Write-through bit, specifies the						   cache write mode:						   0 - Copy-back mode						   1 - Write-through mode *//* Page Table Entry Assistance register - PTEA */#define SH7750_PTEA_REGOFS    0x000034	/* offset */#define SH7750_PTEA           SH7750_P4_REG32(SH7750_PTEA_REGOFS)#define SH7750_PTEA_A7        SH7750_A7_REG32(SH7750_PTEA_REGOFS)#define SH7750_PTEA_TC        0x00000008	/* Timing Control bit						   0 - use area 5 wait states						   1 - use area 6 wait states */#define SH7750_PTEA_SA        0x00000007	/* Space Attribute bits: */#define SH7750_PTEA_SA_UNDEF  0x00000000	/*    0 - undefined */#define SH7750_PTEA_SA_IOVAR  0x00000001	/*    1 - variable-size I/O space */#define SH7750_PTEA_SA_IO8    0x00000002	/*    2 - 8-bit I/O space */#define SH7750_PTEA_SA_IO16   0x00000003	/*    3 - 16-bit I/O space */#define SH7750_PTEA_SA_CMEM8  0x00000004	/*    4 - 8-bit common memory space */#define SH7750_PTEA_SA_CMEM16 0x00000005	/*    5 - 16-bit common memory space */#define SH7750_PTEA_SA_AMEM8  0x00000006	/*    6 - 8-bit attr memory space */#define SH7750_PTEA_SA_AMEM16 0x00000007	/*    7 - 16-bit attr memory space *//* Translation table base register */#define SH7750_TTB_REGOFS     0x000008	/* offset */#define SH7750_TTB            SH7750_P4_REG32(SH7750_TTB_REGOFS)#define SH7750_TTB_A7         SH7750_A7_REG32(SH7750_TTB_REGOFS)/* TLB exeption address register - TEA */#define SH7750_TEA_REGOFS     0x00000c	/* offset */#define SH7750_TEA            SH7750_P4_REG32(SH7750_TEA_REGOFS)#define SH7750_TEA_A7         SH7750_A7_REG32(SH7750_TEA_REGOFS)/* MMU control register - MMUCR */#define SH7750_MMUCR_REGOFS   0x000010	/* offset */#define SH7750_MMUCR          SH7750_P4_REG32(SH7750_MMUCR_REGOFS)#define SH7750_MMUCR_A7       SH7750_A7_REG32(SH7750_MMUCR_REGOFS)#define SH7750_MMUCR_AT       0x00000001	/* Address translation bit */#define SH7750_MMUCR_TI       0x00000004	/* TLB invalidate */#define SH7750_MMUCR_SV       0x00000100	/* Single Virtual Mode bit */#define SH7750_MMUCR_SQMD     0x00000200	/* Store Queue Mode bit */#define SH7750_MMUCR_URC      0x0000FC00	/* UTLB Replace Counter */#define SH7750_MMUCR_URC_S    10#define SH7750_MMUCR_URB      0x00FC0000	/* UTLB Replace Boundary */#define SH7750_MMUCR_URB_S    18#define SH7750_MMUCR_LRUI     0xFC000000	/* Least Recently Used ITLB */#define SH7750_MMUCR_LRUI_S   26/* * Cache registers *   IC -- instructions cache *   OC -- operand cache *//* Cache Control Register - CCR */#define SH7750_CCR_REGOFS     0x00001c	/* offset */#define SH7750_CCR            SH7750_P4_REG32(SH7750_CCR_REGOFS)#define SH7750_CCR_A7         SH7750_A7_REG32(SH7750_CCR_REGOFS)#define SH7750_CCR_IIX      0x00008000	/* IC index enable bit */#define SH7750_CCR_ICI      0x00000800	/* IC invalidation bit:					   set it to clear IC */#define SH7750_CCR_ICE      0x00000100	/* IC enable bit */#define SH7750_CCR_OIX      0x00000080	/* OC index enable bit */#define SH7750_CCR_ORA      0x00000020	/* OC RAM enable bit					   if you set OCE = 0,					   you should set ORA = 0 */#define SH7750_CCR_OCI      0x00000008	/* OC invalidation bit */#define SH7750_CCR_CB       0x00000004	/* Copy-back bit for P1 area */#define SH7750_CCR_WT       0x00000002	/* Write-through bit for P0,U0,P3 area */#define SH7750_CCR_OCE      0x00000001	/* OC enable bit *//* Queue address control register 0 - QACR0 */#define SH7750_QACR0_REGOFS   0x000038	/* offset */#define SH7750_QACR0          SH7750_P4_REG32(SH7750_QACR0_REGOFS)#define SH7750_QACR0_A7       SH7750_A7_REG32(SH7750_QACR0_REGOFS)/* Queue address control register 1 - QACR1 */#define SH7750_QACR1_REGOFS   0x00003c	/* offset */#define SH7750_QACR1          SH7750_P4_REG32(SH7750_QACR1_REGOFS)#define SH7750_QACR1_A7       SH7750_A7_REG32(SH7750_QACR1_REGOFS)/* * Exeption-related registers *//* Immediate data for TRAPA instuction - TRA */#define SH7750_TRA_REGOFS     0x000020	/* offset */#define SH7750_TRA            SH7750_P4_REG32(SH7750_TRA_REGOFS)#define SH7750_TRA_A7         SH7750_A7_REG32(SH7750_TRA_REGOFS)#define SH7750_TRA_IMM      0x000003fd	/* Immediate data operand */#define SH7750_TRA_IMM_S    2/* Exeption event register - EXPEVT */#define SH7750_EXPEVT_REGOFS  0x000024#define SH7750_EXPEVT         SH7750_P4_REG32(SH7750_EXPEVT_REGOFS)#define SH7750_EXPEVT_A7      SH7750_A7_REG32(SH7750_EXPEVT_REGOFS)#define SH7750_EXPEVT_EX      0x00000fff	/* Exeption code */#define SH7750_EXPEVT_EX_S    0/* Interrupt event register */#define SH7750_INTEVT_REGOFS  0x000028#define SH7750_INTEVT         SH7750_P4_REG32(SH7750_INTEVT_REGOFS)#define SH7750_INTEVT_A7      SH7750_A7_REG32(SH7750_INTEVT_REGOFS)#define SH7750_INTEVT_EX    0x00000fff	/* Exeption code */#define SH7750_INTEVT_EX_S  0/* * Exception/interrupt codes */#define SH7750_EVT_TO_NUM(evt)  ((evt) >> 5)/* Reset exception category */#define SH7750_EVT_POWER_ON_RST        0x000	/* Power-on reset */#define SH7750_EVT_MANUAL_RST          0x020	/* Manual reset */#define SH7750_EVT_TLB_MULT_HIT        0x140	/* TLB multiple-hit exception *//* General exception category */#define SH7750_EVT_USER_BREAK          0x1E0	/* User break */#define SH7750_EVT_IADDR_ERR           0x0E0	/* Instruction address error */#define SH7750_EVT_TLB_READ_MISS       0x040	/* ITLB miss exception /						   DTLB miss exception (read) */#define SH7750_EVT_TLB_READ_PROTV      0x0A0	/* ITLB protection violation /						   DTLB protection violation (read) */#define SH7750_EVT_ILLEGAL_INSTR       0x180	/* General Illegal Instruction						   exception */#define SH7750_EVT_SLOT_ILLEGAL_INSTR  0x1A0	/* Slot Illegal Instruction						   exception */#define SH7750_EVT_FPU_DISABLE         0x800	/* General FPU disable exception */#define SH7750_EVT_SLOT_FPU_DISABLE    0x820	/* Slot FPU disable exception */#define SH7750_EVT_DATA_READ_ERR       0x0E0	/* Data address error (read) */#define SH7750_EVT_DATA_WRITE_ERR      0x100	/* Data address error (write) */#define SH7750_EVT_DTLB_WRITE_MISS     0x060	/* DTLB miss exception (write) */#define SH7750_EVT_DTLB_WRITE_PROTV    0x0C0	/* DTLB protection violation						   exception (write) */#define SH7750_EVT_FPU_EXCEPTION       0x120	/* FPU exception */#define SH7750_EVT_INITIAL_PGWRITE     0x080	/* Initial Page Write exception */#define SH7750_EVT_TRAPA               0x160	/* Unconditional trap (TRAPA) *//* Interrupt exception category */#define SH7750_EVT_NMI                 0x1C0	/* Non-maskable interrupt */#define SH7750_EVT_IRQ0                0x200	/* External Interrupt 0 */#define SH7750_EVT_IRQ1                0x220	/* External Interrupt 1 */#define SH7750_EVT_IRQ2                0x240	/* External Interrupt 2 */#define SH7750_EVT_IRQ3                0x260	/* External Interrupt 3 */#define SH7750_EVT_IRQ4                0x280	/* External Interrupt 4 */#define SH7750_EVT_IRQ5                0x2A0	/* External Interrupt 5 */#define SH7750_EVT_IRQ6                0x2C0	/* External Interrupt 6 */#define SH7750_EVT_IRQ7                0x2E0	/* External Interrupt 7 */#define SH7750_EVT_IRQ8                0x300	/* External Interrupt 8 */#define SH7750_EVT_IRQ9                0x320	/* External Interrupt 9 */#define SH7750_EVT_IRQA                0x340	/* External Interrupt A */#define SH7750_EVT_IRQB                0x360	/* External Interrupt B */#define SH7750_EVT_IRQC                0x380	/* External Interrupt C */#define SH7750_EVT_IRQD                0x3A0	/* External Interrupt D */#define SH7750_EVT_IRQE                0x3C0	/* External Interrupt E *//* Peripheral Module Interrupts - Timer Unit (TMU) */#define SH7750_EVT_TUNI0               0x400	/* TMU Underflow Interrupt 0 */#define SH7750_EVT_TUNI1               0x420	/* TMU Underflow Interrupt 1 */#define SH7750_EVT_TUNI2               0x440	/* TMU Underflow Interrupt 2 */#define SH7750_EVT_TICPI2              0x460	/* TMU Input Capture Interrupt 2 *//* Peripheral Module Interrupts - Real-Time Clock (RTC) */#define SH7750_EVT_RTC_ATI             0x480	/* Alarm Interrupt Request */#define SH7750_EVT_RTC_PRI             0x4A0	/* Periodic Interrupt Request */#define SH7750_EVT_RTC_CUI             0x4C0	/* Carry Interrupt Request *//* Peripheral Module Interrupts - Serial Communication Interface (SCI) */#define SH7750_EVT_SCI_ERI             0x4E0	/* Receive Error */#define SH7750_EVT_SCI_RXI             0x500	/* Receive Data Register Full */#define SH7750_EVT_SCI_TXI             0x520	/* Transmit Data Register Empty */#define SH7750_EVT_SCI_TEI             0x540	/* Transmit End *//* Peripheral Module Interrupts - Watchdog Timer (WDT) */#define SH7750_EVT_WDT_ITI             0x560	/* Interval Timer Interrupt						   (used when WDT operates in						   interval timer mode) */