case GT_PCI0_BS_CS20:    case GT_PCI0_BS_CS3BT:    case GT_PCI1_IACK:    case GT_PCI0_BARE:    case GT_PCI0_PREFMBR:    case GT_PCI0_SCS10_BAR:    case GT_PCI0_SCS32_BAR:    case GT_PCI0_CS20_BAR:    case GT_PCI0_CS3BT_BAR:    case GT_PCI0_SSCS10_BAR:    case GT_PCI0_SSCS32_BAR:    case GT_PCI0_SCS3BT_BAR:    case GT_PCI1_CMD:    case GT_PCI1_TOR:    case GT_PCI1_BS_SCS10:    case GT_PCI1_BS_SCS32:    case GT_PCI1_BS_CS20:    case GT_PCI1_BS_CS3BT:    case GT_PCI1_BARE:    case GT_PCI1_PREFMBR:    case GT_PCI1_SCS10_BAR:    case GT_PCI1_SCS32_BAR:    case GT_PCI1_CS20_BAR:    case GT_PCI1_CS3BT_BAR:    case GT_PCI1_SSCS10_BAR:    case GT_PCI1_SSCS32_BAR:    case GT_PCI1_SCS3BT_BAR:    case GT_PCI1_CFGADDR:    case GT_PCI1_CFGDATA:        val = s->regs[saddr];        break;    /* Interrupts */    case GT_INTRCAUSE:        val = s->regs[saddr];        dprintf("INTRCAUSE %x\n", val);        break;    case GT_INTRMASK:        val = s->regs[saddr];        dprintf("INTRMASK %x\n", val);        break;    case GT_PCI0_ICMASK:        val = s->regs[saddr];        dprintf("ICMASK %x\n", val);        break;    case GT_PCI0_SERR0MASK:        val = s->regs[saddr];        dprintf("SERR0MASK %x\n", val);        break;    /* Reserved when only PCI_0 is configured. */    case GT_HINTRCAUSE:    case GT_CPU_INTSEL:    case GT_PCI0_INTSEL:    case GT_HINTRMASK:    case GT_PCI0_HICMASK:    case GT_PCI1_SERR1MASK:        val = s->regs[saddr];        break;    default:        val = s->regs[saddr];        dprintf ("Bad register offset 0x%x\n", (int)addr);        break;    }    if (!(s->regs[GT_PCI0_CMD] & 1))        val = bswap32(val);    return val;}static CPUWriteMemoryFunc *gt64120_write[] = {    &gt64120_writel,    &gt64120_writel,    &gt64120_writel,};static CPUReadMemoryFunc *gt64120_read[] = {    &gt64120_readl,    &gt64120_readl,    &gt64120_readl,};static int pci_gt64120_map_irq(PCIDevice *pci_dev, int irq_num){    int slot;    slot = (pci_dev->devfn >> 3);    switch (slot) {      /* PIIX4 USB */      case 10:        return 3;      /* AMD 79C973 Ethernet */      case 11:        return 1;      /* Crystal 4281 Sound */      case 12:        return 2;      /* PCI slot 1 to 4 */      case 18 ... 21:        return ((slot - 18) + irq_num) & 0x03;      /* Unknown device, don't do any translation */      default:        return irq_num;    }}extern PCIDevice *piix4_dev;static int pci_irq_levels[4];static void pci_gt64120_set_irq(qemu_irq *pic, int irq_num, int level){    int i, pic_irq, pic_level;    pci_irq_levels[irq_num] = level;    /* now we change the pic irq level according to the piix irq mappings */    /* XXX: optimize */    pic_irq = piix4_dev->config[0x60 + irq_num];    if (pic_irq < 16) {        /* The pic level is the logical OR of all the PCI irqs mapped           to it */        pic_level = 0;        for (i = 0; i < 4; i++) {            if (pic_irq == piix4_dev->config[0x60 + i])                pic_level |= pci_irq_levels[i];        }        qemu_set_irq(pic[pic_irq], pic_level);    }}static void gt64120_reset(void *opaque){    GT64120State *s = opaque;    /* FIXME: Malta specific hw assumptions ahead */    /* CPU Configuration */#ifdef TARGET_WORDS_BIGENDIAN    s->regs[GT_CPU]           = 0x00000000;#else    s->regs[GT_CPU]           = 0x00001000;#endif    s->regs[GT_MULTI]         = 0x00000003;    /* CPU Address decode */    s->regs[GT_SCS10LD]       = 0x00000000;    s->regs[GT_SCS10HD]       = 0x00000007;    s->regs[GT_SCS32LD]       = 0x00000008;    s->regs[GT_SCS32HD]       = 0x0000000f;    s->regs[GT_CS20LD]        = 0x000000e0;    s->regs[GT_CS20HD]        = 0x00000070;    s->regs[GT_CS3BOOTLD]     = 0x000000f8;    s->regs[GT_CS3BOOTHD]     = 0x0000007f;    s->regs[GT_PCI0IOLD]      = 0x00000080;    s->regs[GT_PCI0IOHD]      = 0x0000000f;    s->regs[GT_PCI0M0LD]      = 0x00000090;    s->regs[GT_PCI0M0HD]      = 0x0000001f;    s->regs[GT_ISD]           = 0x000000a0;    s->regs[GT_PCI0M1LD]      = 0x00000790;    s->regs[GT_PCI0M1HD]      = 0x0000001f;    s->regs[GT_PCI1IOLD]      = 0x00000100;    s->regs[GT_PCI1IOHD]      = 0x0000000f;    s->regs[GT_PCI1M0LD]      = 0x00000110;    s->regs[GT_PCI1M0HD]      = 0x0000001f;    s->regs[GT_PCI1M1LD]      = 0x00000120;    s->regs[GT_PCI1M1HD]      = 0x0000002f;    s->regs[GT_SCS10AR]       = 0x00000000;    s->regs[GT_SCS32AR]       = 0x00000008;    s->regs[GT_CS20R]         = 0x000000e0;    s->regs[GT_CS3BOOTR]      = 0x000000f8;    s->regs[GT_PCI0IOREMAP]   = 0x00000080;    s->regs[GT_PCI0M0REMAP]   = 0x00000090;    s->regs[GT_PCI0M1REMAP]   = 0x00000790;    s->regs[GT_PCI1IOREMAP]   = 0x00000100;    s->regs[GT_PCI1M0REMAP]   = 0x00000110;    s->regs[GT_PCI1M1REMAP]   = 0x00000120;    /* CPU Error Report */    s->regs[GT_CPUERR_ADDRLO] = 0x00000000;    s->regs[GT_CPUERR_ADDRHI] = 0x00000000;    s->regs[GT_CPUERR_DATALO] = 0xffffffff;    s->regs[GT_CPUERR_DATAHI] = 0xffffffff;    s->regs[GT_CPUERR_PARITY] = 0x000000ff;    /* CPU Sync Barrier */    s->regs[GT_PCI0SYNC]      = 0x00000000;    s->regs[GT_PCI1SYNC]      = 0x00000000;    /* SDRAM and Device Address Decode */    s->regs[GT_SCS0LD]        = 0x00000000;    s->regs[GT_SCS0HD]        = 0x00000007;    s->regs[GT_SCS1LD]        = 0x00000008;    s->regs[GT_SCS1HD]        = 0x0000000f;    s->regs[GT_SCS2LD]        = 0x00000010;    s->regs[GT_SCS2HD]        = 0x00000017;    s->regs[GT_SCS3LD]        = 0x00000018;    s->regs[GT_SCS3HD]        = 0x0000001f;    s->regs[GT_CS0LD]         = 0x000000c0;    s->regs[GT_CS0HD]         = 0x000000c7;    s->regs[GT_CS1LD]         = 0x000000c8;    s->regs[GT_CS1HD]         = 0x000000cf;    s->regs[GT_CS2LD]         = 0x000000d0;    s->regs[GT_CS2HD]         = 0x000000df;    s->regs[GT_CS3LD]         = 0x000000f0;    s->regs[GT_CS3HD]         = 0x000000fb;    s->regs[GT_BOOTLD]        = 0x000000fc;    s->regs[GT_BOOTHD]        = 0x000000ff;    s->regs[GT_ADERR]         = 0xffffffff;    /* SDRAM Configuration */    s->regs[GT_SDRAM_CFG]     = 0x00000200;    s->regs[GT_SDRAM_OPMODE]  = 0x00000000;    s->regs[GT_SDRAM_BM]      = 0x00000007;    s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;    /* SDRAM Parameters */    s->regs[GT_SDRAM_B0]      = 0x00000005;    s->regs[GT_SDRAM_B1]      = 0x00000005;    s->regs[GT_SDRAM_B2]      = 0x00000005;    s->regs[GT_SDRAM_B3]      = 0x00000005;    /* ECC */    s->regs[GT_ECC_ERRDATALO] = 0x00000000;    s->regs[GT_ECC_ERRDATAHI] = 0x00000000;    s->regs[GT_ECC_MEM]       = 0x00000000;    s->regs[GT_ECC_CALC]      = 0x00000000;    s->regs[GT_ECC_ERRADDR]   = 0x00000000;    /* Device Parameters */    s->regs[GT_DEV_B0]        = 0x386fffff;    s->regs[GT_DEV_B1]        = 0x386fffff;    s->regs[GT_DEV_B2]        = 0x386fffff;    s->regs[GT_DEV_B3]        = 0x386fffff;    s->regs[GT_DEV_BOOT]      = 0x146fffff;    /* DMA registers are all zeroed at reset */    /* Timer/Counter */    s->regs[GT_TC0]           = 0xffffffff;    s->regs[GT_TC1]           = 0x00ffffff;    s->regs[GT_TC2]           = 0x00ffffff;    s->regs[GT_TC3]           = 0x00ffffff;    s->regs[GT_TC_CONTROL]    = 0x00000000;    /* PCI Internal */#ifdef TARGET_WORDS_BIGENDIAN    s->regs[GT_PCI0_CMD]      = 0x00000000;#else    s->regs[GT_PCI0_CMD]      = 0x00010001;#endif    s->regs[GT_PCI0_TOR]      = 0x0000070f;    s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;    s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;    s->regs[GT_PCI0_BS_CS20]  = 0x01fff000;    s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;    s->regs[GT_PCI1_IACK]     = 0x00000000;    s->regs[GT_PCI0_IACK]     = 0x00000000;    s->regs[GT_PCI0_BARE]     = 0x0000000f;    s->regs[GT_PCI0_PREFMBR]  = 0x00000040;    s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;    s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;    s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;    s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;    s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;    s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;    s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;#ifdef TARGET_WORDS_BIGENDIAN    s->regs[GT_PCI1_CMD]      = 0x00000000;#else    s->regs[GT_PCI1_CMD]      = 0x00010001;#endif    s->regs[GT_PCI1_TOR]      = 0x0000070f;    s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;    s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;    s->regs[GT_PCI1_BS_CS20]  = 0x01fff000;    s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;    s->regs[GT_PCI1_BARE]     = 0x0000000f;    s->regs[GT_PCI1_PREFMBR]  = 0x00000040;    s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;    s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;    s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;    s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;    s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;    s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;    s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;    s->regs[GT_PCI1_CFGADDR]  = 0x00000000;    s->regs[GT_PCI1_CFGDATA]  = 0x00000000;    s->regs[GT_PCI0_CFGADDR]  = 0x00000000;    s->regs[GT_PCI0_CFGDATA]  = 0x00000000;    /* Interrupt registers are all zeroed at reset */    gt64120_isd_mapping(s);    gt64120_pci_mapping(s);}static uint32_t gt64120_read_config(PCIDevice *d, uint32_t address, int len){    return pci_default_read_config(d, address, len);}static void gt64120_write_config(PCIDevice *d, uint32_t address, uint32_t val,                                 int len){    pci_default_write_config(d, address, val, len);}static void gt64120_save(QEMUFile* f, void *opaque){    PCIDevice *d = opaque;    pci_device_save(d, f);}static int gt64120_load(QEMUFile* f, void *opaque, int version_id){    PCIDevice *d = opaque;    int ret;    if (version_id != 1)        return -EINVAL;    ret = pci_device_load(d, f);    if (ret < 0)        return ret;    return 0;}PCIBus *pci_gt64120_init(qemu_irq *pic){    GT64120State *s;    PCIDevice *d;    (void)&pci_host_data_writeb; /* avoid warning */    (void)&pci_host_data_writew; /* avoid warning */    (void)&pci_host_data_readb; /* avoid warning */    (void)&pci_host_data_readw; /* avoid warning */    s = qemu_mallocz(sizeof(GT64120State));    s->pci = qemu_mallocz(sizeof(GT64120PCIState));    s->pci->bus = pci_register_bus(pci_gt64120_set_irq, pci_gt64120_map_irq,                                   pic, 144, 4);    s->ISD_handle = cpu_register_io_memory(0, gt64120_read, gt64120_write, s);    d = pci_register_device(s->pci->bus, "GT64120 PCI Bus", sizeof(PCIDevice),                            0, gt64120_read_config, gt64120_write_config);    /* FIXME: Malta specific hw assumptions ahead */    d->config[0x00] = 0xab; /* vendor_id */    d->config[0x01] = 0x11;    d->config[0x02] = 0x20; /* device_id */    d->config[0x03] = 0x46;    d->config[0x04] = 0x00;    d->config[0x05] = 0x00;    d->config[0x06] = 0x80;    d->config[0x07] = 0x02;    d->config[0x08] = 0x10;    d->config[0x09] = 0x00;    d->config[0x0A] = 0x00;    d->config[0x0B] = 0x06;    d->config[0x10] = 0x08;    d->config[0x14] = 0x08;    d->config[0x17] = 0x01;    d->config[0x1B] = 0x1c;    d->config[0x1F] = 0x1f;    d->config[0x23] = 0x14;    d->config[0x24] = 0x01;    d->config[0x27] = 0x14;    d->config[0x3D] = 0x01;    gt64120_reset(s);    register_savevm("GT64120 PCI Bus", 0, 1, gt64120_save, gt64120_load, d);    return s->pci->bus;}