initrd_filename);                exit(1);            }        } else {            initrd_base = 0;            initrd_size = 0;        }        env->gpr[4] = initrd_base;        env->gpr[5] = initrd_size;        ppc_boot_device = 'm';        if (kernel_cmdline != NULL) {            len = strlen(kernel_cmdline);            bdloc -= ((len + 255) & ~255);            memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1);            env->gpr[6] = bdloc;            env->gpr[7] = bdloc + len;        } else {            env->gpr[6] = 0;            env->gpr[7] = 0;        }        env->nip = KERNEL_LOAD_ADDR;    } else {        kernel_base = 0;        kernel_size = 0;        initrd_base = 0;        initrd_size = 0;        bdloc = 0;    }#ifdef DEBUG_BOARD_INIT    printf("%s: Done\n", __func__);#endif    printf("bdloc %016lx %s\n",           (unsigned long)bdloc, (char *)(phys_ram_base + bdloc));}QEMUMachine ref405ep_machine = {    "ref405ep",    "ref405ep",    ref405ep_init,};/*****************************************************************************//* AMCC Taihu evaluation board *//* - PowerPC 405EP processor * - SDRAM               128 MB at 0x00000000 * - Boot flash          2 MB   at 0xFFE00000 * - Application flash   32 MB  at 0xFC000000 * - 2 serial ports * - 2 ethernet PHY * - 1 USB 1.1 device    0x50000000 * - 1 LCD display       0x50100000 * - 1 CPLD              0x50100000 * - 1 I2C EEPROM * - 1 I2C thermal sensor * - a set of LEDs * - bit-bang SPI port using GPIOs * - 1 EBC interface connector 0 0x50200000 * - 1 cardbus controller + expansion slot. * - 1 PCI expansion slot. */typedef struct taihu_cpld_t taihu_cpld_t;struct taihu_cpld_t {    uint32_t base;    uint8_t reg0;    uint8_t reg1;};static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr){    taihu_cpld_t *cpld;    uint32_t ret;    cpld = opaque;    addr -= cpld->base;    switch (addr) {    case 0x0:        ret = cpld->reg0;        break;    case 0x1:        ret = cpld->reg1;        break;    default:        ret = 0;        break;    }    return ret;}static void taihu_cpld_writeb (void *opaque,                               target_phys_addr_t addr, uint32_t value){    taihu_cpld_t *cpld;    cpld = opaque;    addr -= cpld->base;    switch (addr) {    case 0x0:        /* Read only */        break;    case 0x1:        cpld->reg1 = value;        break;    default:        break;    }}static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr){    uint32_t ret;    ret = taihu_cpld_readb(opaque, addr) << 8;    ret |= taihu_cpld_readb(opaque, addr + 1);    return ret;}static void taihu_cpld_writew (void *opaque,                               target_phys_addr_t addr, uint32_t value){    taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);    taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);}static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr){    uint32_t ret;    ret = taihu_cpld_readb(opaque, addr) << 24;    ret |= taihu_cpld_readb(opaque, addr + 1) << 16;    ret |= taihu_cpld_readb(opaque, addr + 2) << 8;    ret |= taihu_cpld_readb(opaque, addr + 3);    return ret;}static void taihu_cpld_writel (void *opaque,                               target_phys_addr_t addr, uint32_t value){    taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);    taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);    taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);    taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);}static CPUReadMemoryFunc *taihu_cpld_read[] = {    &taihu_cpld_readb,    &taihu_cpld_readw,    &taihu_cpld_readl,};static CPUWriteMemoryFunc *taihu_cpld_write[] = {    &taihu_cpld_writeb,    &taihu_cpld_writew,    &taihu_cpld_writel,};static void taihu_cpld_reset (void *opaque){    taihu_cpld_t *cpld;    cpld = opaque;    cpld->reg0 = 0x01;    cpld->reg1 = 0x80;}static void taihu_cpld_init (uint32_t base){    taihu_cpld_t *cpld;    int cpld_memory;    cpld = qemu_mallocz(sizeof(taihu_cpld_t));    if (cpld != NULL) {        cpld->base = base;        cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,                                             taihu_cpld_write, cpld);        cpu_register_physical_memory(base, 0x00000100, cpld_memory);        taihu_cpld_reset(cpld);        qemu_register_reset(&taihu_cpld_reset, cpld);    }}static void taihu_405ep_init(int ram_size, int vga_ram_size,                             const char *boot_device, DisplayState *ds,                             const char *kernel_filename,                             const char *kernel_cmdline,                             const char *initrd_filename,                             const char *cpu_model){    char buf[1024];    CPUPPCState *env;    qemu_irq *pic;    ram_addr_t bios_offset;    target_phys_addr_t ram_bases[2], ram_sizes[2];    target_ulong bios_size;    target_ulong kernel_base, kernel_size, initrd_base, initrd_size;    int linux_boot;    int fl_idx, fl_sectors;    int ppc_boot_device = boot_device[0];    int index;    /* RAM is soldered to the board so the size cannot be changed */    ram_bases[0] = 0x00000000;    ram_sizes[0] = 0x04000000;    ram_bases[1] = 0x04000000;    ram_sizes[1] = 0x04000000;#ifdef DEBUG_BOARD_INIT    printf("%s: register cpu\n", __func__);#endif    env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset,                        kernel_filename == NULL ? 0 : 1);    /* allocate and load BIOS */#ifdef DEBUG_BOARD_INIT    printf("%s: register BIOS\n", __func__);#endif    fl_idx = 0;#if defined(USE_FLASH_BIOS)    index = drive_get_index(IF_PFLASH, 0, fl_idx);    if (index != -1) {        bios_size = bdrv_getlength(drives_table[index].bdrv);        /* XXX: should check that size is 2MB */        //        bios_size = 2 * 1024 * 1024;        fl_sectors = (bios_size + 65535) >> 16;#ifdef DEBUG_BOARD_INIT        printf("Register parallel flash %d size " ADDRX " at offset %08lx "               " addr " ADDRX " '%s' %d\n",               fl_idx, bios_size, bios_offset, -bios_size,               bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);#endif        pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,                              drives_table[index].bdrv, 65536, fl_sectors, 4,                              0x0001, 0x22DA, 0x0000, 0x0000);        fl_idx++;    } else#endif    {#ifdef DEBUG_BOARD_INIT        printf("Load BIOS from file\n");#endif        if (bios_name == NULL)            bios_name = BIOS_FILENAME;        snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);        bios_size = load_image(buf, phys_ram_base + bios_offset);        if (bios_size < 0 || bios_size > BIOS_SIZE) {            fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);            exit(1);        }        bios_size = (bios_size + 0xfff) & ~0xfff;        cpu_register_physical_memory((uint32_t)(-bios_size),                                     bios_size, bios_offset | IO_MEM_ROM);    }    bios_offset += bios_size;    /* Register Linux flash */    index = drive_get_index(IF_PFLASH, 0, fl_idx);    if (index != -1) {        bios_size = bdrv_getlength(drives_table[index].bdrv);        /* XXX: should check that size is 32MB */        bios_size = 32 * 1024 * 1024;        fl_sectors = (bios_size + 65535) >> 16;#ifdef DEBUG_BOARD_INIT        printf("Register parallel flash %d size " ADDRX " at offset %08lx "               " addr " ADDRX " '%s'\n",               fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,               bdrv_get_device_name(drives_table[index].bdrv));#endif        pflash_cfi02_register(0xfc000000, bios_offset,                              drives_table[index].bdrv, 65536, fl_sectors, 4,                              0x0001, 0x22DA, 0x0000, 0x0000);        fl_idx++;    }    /* Register CLPD & LCD display */#ifdef DEBUG_BOARD_INIT    printf("%s: register CPLD\n", __func__);#endif    taihu_cpld_init(0x50100000);    /* Load kernel */    linux_boot = (kernel_filename != NULL);    if (linux_boot) {#ifdef DEBUG_BOARD_INIT        printf("%s: load kernel\n", __func__);#endif        kernel_base = KERNEL_LOAD_ADDR;        /* now we can load the kernel */        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);        if (kernel_size < 0) {            fprintf(stderr, "qemu: could not load kernel '%s'\n",                    kernel_filename);            exit(1);        }        /* load initrd */        if (initrd_filename) {            initrd_base = INITRD_LOAD_ADDR;            initrd_size = load_image(initrd_filename,                                     phys_ram_base + initrd_base);            if (initrd_size < 0) {                fprintf(stderr,                        "qemu: could not load initial ram disk '%s'\n",                        initrd_filename);                exit(1);            }        } else {            initrd_base = 0;            initrd_size = 0;        }        ppc_boot_device = 'm';    } else {        kernel_base = 0;        kernel_size = 0;        initrd_base = 0;        initrd_size = 0;    }#ifdef DEBUG_BOARD_INIT    printf("%s: Done\n", __func__);#endif}QEMUMachine taihu_machine = {    "taihu",    "taihu",    taihu_405ep_init,};