/* * QEMU 8259 interrupt controller emulation * * Copyright (c) 2003-2004 Fabrice Bellard * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */#include "hw.h"#include "pc.h"#include "isa.h"#include "console.h"/* debug PIC *///#define DEBUG_PIC//#define DEBUG_IRQ_LATENCY//#define DEBUG_IRQ_COUNTtypedef struct PicState {    uint8_t last_irr; /* edge detection */    uint8_t irr; /* interrupt request register */    uint8_t imr; /* interrupt mask register */    uint8_t isr; /* interrupt service register */    uint8_t priority_add; /* highest irq priority */    uint8_t irq_base;    uint8_t read_reg_select;    uint8_t poll;    uint8_t special_mask;    uint8_t init_state;    uint8_t auto_eoi;    uint8_t rotate_on_auto_eoi;    uint8_t special_fully_nested_mode;    uint8_t init4; /* true if 4 byte init */    uint8_t single_mode; /* true if slave pic is not initialized */    uint8_t elcr; /* PIIX edge/trigger selection*/    uint8_t elcr_mask;    PicState2 *pics_state;} PicState;struct PicState2 {    /* 0 is master pic, 1 is slave pic */    /* XXX: better separation between the two pics */    PicState pics[2];    qemu_irq parent_irq;    void *irq_request_opaque;    /* IOAPIC callback support */    SetIRQFunc *alt_irq_func;    void *alt_irq_opaque;};#if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)static int irq_level[16];#endif#ifdef DEBUG_IRQ_COUNTstatic uint64_t irq_count[16];#endif/* set irq level. If an edge is detected, then the IRR is set to 1 */static inline void pic_set_irq1(PicState *s, int irq, int level){    int mask;    mask = 1 << irq;    if (s->elcr & mask) {        /* level triggered */        if (level) {            s->irr |= mask;            s->last_irr |= mask;        } else {            s->irr &= ~mask;            s->last_irr &= ~mask;        }    } else {        /* edge triggered */        if (level) {            if ((s->last_irr & mask) == 0)                s->irr |= mask;            s->last_irr |= mask;        } else {            s->last_irr &= ~mask;        }    }}/* return the highest priority found in mask (highest = smallest   number). Return 8 if no irq */static inline int get_priority(PicState *s, int mask){    int priority;    if (mask == 0)        return 8;    priority = 0;    while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)        priority++;    return priority;}/* return the pic wanted interrupt. return -1 if none */static int pic_get_irq(PicState *s){    int mask, cur_priority, priority;    mask = s->irr & ~s->imr;    priority = get_priority(s, mask);    if (priority == 8)        return -1;    /* compute current priority. If special fully nested mode on the       master, the IRQ coming from the slave is not taken into account       for the priority computation. */    mask = s->isr;    if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])        mask &= ~(1 << 2);    cur_priority = get_priority(s, mask);    if (priority < cur_priority) {        /* higher priority found: an irq should be generated */        return (priority + s->priority_add) & 7;    } else {        return -1;    }}/* raise irq to CPU if necessary. must be called every time the active   irq may change *//* XXX: should not export it, but it is needed for an APIC kludge */void pic_update_irq(PicState2 *s){    int irq2, irq;    /* first look at slave pic */    irq2 = pic_get_irq(&s->pics[1]);    if (irq2 >= 0) {        /* if irq request by slave pic, signal master PIC */        pic_set_irq1(&s->pics[0], 2, 1);        pic_set_irq1(&s->pics[0], 2, 0);    }    /* look at requested irq */    irq = pic_get_irq(&s->pics[0]);    if (irq >= 0) {#if defined(DEBUG_PIC)        {            int i;            for(i = 0; i < 2; i++) {                printf("pic%d: imr=%x irr=%x padd=%d\n",                       i, s->pics[i].imr, s->pics[i].irr,                       s->pics[i].priority_add);            }        }        printf("pic: cpu_interrupt\n");#endif        qemu_irq_raise(s->parent_irq);    }/* all targets should do this rather than acking the IRQ in the cpu */#if defined(TARGET_MIPS) || defined(TARGET_PPC)    else {        qemu_irq_lower(s->parent_irq);    }#endif}#ifdef DEBUG_IRQ_LATENCYint64_t irq_time[16];#endifstatic void i8259_set_irq(void *opaque, int irq, int level){    PicState2 *s = opaque;#if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)    if (level != irq_level[irq]) {#if defined(DEBUG_PIC)        printf("i8259_set_irq: irq=%d level=%d\n", irq, level);#endif        irq_level[irq] = level;#ifdef DEBUG_IRQ_COUNT	if (level == 1)	    irq_count[irq]++;#endif    }#endif#ifdef DEBUG_IRQ_LATENCY    if (level) {        irq_time[irq] = qemu_get_clock(vm_clock);    }#endif    pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);    /* used for IOAPIC irqs */    if (s->alt_irq_func)        s->alt_irq_func(s->alt_irq_opaque, irq, level);    pic_update_irq(s);}/* acknowledge interrupt 'irq' */static inline void pic_intack(PicState *s, int irq){    if (s->auto_eoi) {        if (s->rotate_on_auto_eoi)            s->priority_add = (irq + 1) & 7;    } else {        s->isr |= (1 << irq);    }    /* We don't clear a level sensitive interrupt here */    if (!(s->elcr & (1 << irq)))        s->irr &= ~(1 << irq);}int pic_read_irq(PicState2 *s){    int irq, irq2, intno;    irq = pic_get_irq(&s->pics[0]);    if (irq >= 0) {        pic_intack(&s->pics[0], irq);        if (irq == 2) {            irq2 = pic_get_irq(&s->pics[1]);            if (irq2 >= 0) {                pic_intack(&s->pics[1], irq2);            } else {                /* spurious IRQ on slave controller */                irq2 = 7;            }            intno = s->pics[1].irq_base + irq2;            irq = irq2 + 8;        } else {            intno = s->pics[0].irq_base + irq;        }    } else {        /* spurious IRQ on host controller */        irq = 7;        intno = s->pics[0].irq_base + irq;    }    pic_update_irq(s);#ifdef DEBUG_IRQ_LATENCY    printf("IRQ%d latency=%0.3fus\n",           irq,           (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);#endif#if defined(DEBUG_PIC)    printf("pic_interrupt: irq=%d\n", irq);#endif    return intno;}static void pic_reset(void *opaque){    PicState *s = opaque;    s->last_irr = 0;    s->irr = 0;    s->imr = 0;    s->isr = 0;    s->priority_add = 0;    s->irq_base = 0;    s->read_reg_select = 0;    s->poll = 0;    s->special_mask = 0;    s->init_state = 0;    s->auto_eoi = 0;    s->rotate_on_auto_eoi = 0;    s->special_fully_nested_mode = 0;    s->init4 = 0;    s->single_mode = 0;    /* Note: ELCR is not reset */}static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val){    PicState *s = opaque;