int priority, cmd, irq;#ifdef DEBUG_PIC    printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);#endif    addr &= 1;    if (addr == 0) {        if (val & 0x10) {            /* init */            pic_reset(s);            /* deassert a pending interrupt */            qemu_irq_lower(s->pics_state->parent_irq);            s->init_state = 1;            s->init4 = val & 1;            s->single_mode = val & 2;            if (val & 0x08)                hw_error("level sensitive irq not supported");        } else if (val & 0x08) {            if (val & 0x04)                s->poll = 1;            if (val & 0x02)                s->read_reg_select = val & 1;            if (val & 0x40)                s->special_mask = (val >> 5) & 1;        } else {            cmd = val >> 5;            switch(cmd) {            case 0:            case 4:                s->rotate_on_auto_eoi = cmd >> 2;                break;            case 1: /* end of interrupt */            case 5:                priority = get_priority(s, s->isr);                if (priority != 8) {                    irq = (priority + s->priority_add) & 7;                    s->isr &= ~(1 << irq);                    if (cmd == 5)                        s->priority_add = (irq + 1) & 7;                    pic_update_irq(s->pics_state);                }                break;            case 3:                irq = val & 7;                s->isr &= ~(1 << irq);                pic_update_irq(s->pics_state);                break;            case 6:                s->priority_add = (val + 1) & 7;                pic_update_irq(s->pics_state);                break;            case 7:                irq = val & 7;                s->isr &= ~(1 << irq);                s->priority_add = (irq + 1) & 7;                pic_update_irq(s->pics_state);                break;            default:                /* no operation */                break;            }        }    } else {        switch(s->init_state) {        case 0:            /* normal mode */            s->imr = val;            pic_update_irq(s->pics_state);            break;        case 1:            s->irq_base = val & 0xf8;            s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;            break;        case 2:            if (s->init4) {                s->init_state = 3;            } else {                s->init_state = 0;            }            break;        case 3:            s->special_fully_nested_mode = (val >> 4) & 1;            s->auto_eoi = (val >> 1) & 1;            s->init_state = 0;            break;        }    }}static uint32_t pic_poll_read (PicState *s, uint32_t addr1){    int ret;    ret = pic_get_irq(s);    if (ret >= 0) {        if (addr1 >> 7) {            s->pics_state->pics[0].isr &= ~(1 << 2);            s->pics_state->pics[0].irr &= ~(1 << 2);        }        s->irr &= ~(1 << ret);        s->isr &= ~(1 << ret);        if (addr1 >> 7 || ret != 2)            pic_update_irq(s->pics_state);    } else {        ret = 0x07;        pic_update_irq(s->pics_state);    }    return ret;}static uint32_t pic_ioport_read(void *opaque, uint32_t addr1){    PicState *s = opaque;    unsigned int addr;    int ret;    addr = addr1;    addr &= 1;    if (s->poll) {        ret = pic_poll_read(s, addr1);        s->poll = 0;    } else {        if (addr == 0) {            if (s->read_reg_select)                ret = s->isr;            else                ret = s->irr;        } else {            ret = s->imr;        }    }#ifdef DEBUG_PIC    printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);#endif    return ret;}/* memory mapped interrupt status *//* XXX: may be the same than pic_read_irq() */uint32_t pic_intack_read(PicState2 *s){    int ret;    ret = pic_poll_read(&s->pics[0], 0x00);    if (ret == 2)        ret = pic_poll_read(&s->pics[1], 0x80) + 8;    /* Prepare for ISR read */    s->pics[0].read_reg_select = 1;    return ret;}static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val){    PicState *s = opaque;    s->elcr = val & s->elcr_mask;}static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1){    PicState *s = opaque;    return s->elcr;}static void pic_save(QEMUFile *f, void *opaque){    PicState *s = opaque;    qemu_put_8s(f, &s->last_irr);    qemu_put_8s(f, &s->irr);    qemu_put_8s(f, &s->imr);    qemu_put_8s(f, &s->isr);    qemu_put_8s(f, &s->priority_add);    qemu_put_8s(f, &s->irq_base);    qemu_put_8s(f, &s->read_reg_select);    qemu_put_8s(f, &s->poll);    qemu_put_8s(f, &s->special_mask);    qemu_put_8s(f, &s->init_state);    qemu_put_8s(f, &s->auto_eoi);    qemu_put_8s(f, &s->rotate_on_auto_eoi);    qemu_put_8s(f, &s->special_fully_nested_mode);    qemu_put_8s(f, &s->init4);    qemu_put_8s(f, &s->single_mode);    qemu_put_8s(f, &s->elcr);}static int pic_load(QEMUFile *f, void *opaque, int version_id){    PicState *s = opaque;    if (version_id != 1)        return -EINVAL;    qemu_get_8s(f, &s->last_irr);    qemu_get_8s(f, &s->irr);    qemu_get_8s(f, &s->imr);    qemu_get_8s(f, &s->isr);    qemu_get_8s(f, &s->priority_add);    qemu_get_8s(f, &s->irq_base);    qemu_get_8s(f, &s->read_reg_select);    qemu_get_8s(f, &s->poll);    qemu_get_8s(f, &s->special_mask);    qemu_get_8s(f, &s->init_state);    qemu_get_8s(f, &s->auto_eoi);    qemu_get_8s(f, &s->rotate_on_auto_eoi);    qemu_get_8s(f, &s->special_fully_nested_mode);    qemu_get_8s(f, &s->init4);    qemu_get_8s(f, &s->single_mode);    qemu_get_8s(f, &s->elcr);    return 0;}/* XXX: add generic master/slave system */static void pic_init1(int io_addr, int elcr_addr, PicState *s){    register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);    register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);    if (elcr_addr >= 0) {        register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);        register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);    }    register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);    qemu_register_reset(pic_reset, s);}void pic_info(void){    int i;    PicState *s;    if (!isa_pic)        return;    for(i=0;i<2;i++) {        s = &isa_pic->pics[i];        term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",                    i, s->irr, s->imr, s->isr, s->priority_add,                    s->irq_base, s->read_reg_select, s->elcr,                    s->special_fully_nested_mode);    }}void irq_info(void){#ifndef DEBUG_IRQ_COUNT    term_printf("irq statistic code not compiled.\n");#else    int i;    int64_t count;    term_printf("IRQ statistics:\n");    for (i = 0; i < 16; i++) {        count = irq_count[i];        if (count > 0)            term_printf("%2d: %" PRId64 "\n", i, count);    }#endif}qemu_irq *i8259_init(qemu_irq parent_irq){    PicState2 *s;    s = qemu_mallocz(sizeof(PicState2));    if (!s)        return NULL;    pic_init1(0x20, 0x4d0, &s->pics[0]);    pic_init1(0xa0, 0x4d1, &s->pics[1]);    s->pics[0].elcr_mask = 0xf8;    s->pics[1].elcr_mask = 0xde;    s->parent_irq = parent_irq;    s->pics[0].pics_state = s;    s->pics[1].pics_state = s;    isa_pic = s;    return qemu_allocate_irqs(i8259_set_irq, s, 16);}void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,                          void *alt_irq_opaque){    s->alt_irq_func = alt_irq_func;    s->alt_irq_opaque = alt_irq_opaque;}