?? ppc405_uc.c
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__func__, sdram_base(bcr), sdram_size(bcr));#endif cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr), sdram_base(bcr) | IO_MEM_RAM); }}static void sdram_map_bcr (ppc4xx_sdram_t *sdram){ int i; for (i = 0; i < sdram->nbanks; i++) { if (sdram->ram_sizes[i] != 0) { sdram_set_bcr(&sdram->bcr[i], sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), 1); } else { sdram_set_bcr(&sdram->bcr[i], 0x00000000, 0); } }}static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram){ int i; for (i = 0; i < sdram->nbanks; i++) {#ifdef DEBUG_SDRAM printf("%s: Unmap RAM area " PADDRX " " ADDRX "\n", __func__, sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]));#endif cpu_register_physical_memory(sdram_base(sdram->bcr[i]), sdram_size(sdram->bcr[i]), IO_MEM_UNASSIGNED); }}static target_ulong dcr_read_sdram (void *opaque, int dcrn){ ppc4xx_sdram_t *sdram; target_ulong ret; sdram = opaque; switch (dcrn) { case SDRAM0_CFGADDR: ret = sdram->addr; break; case SDRAM0_CFGDATA: switch (sdram->addr) { case 0x00: /* SDRAM_BESR0 */ ret = sdram->besr0; break; case 0x08: /* SDRAM_BESR1 */ ret = sdram->besr1; break; case 0x10: /* SDRAM_BEAR */ ret = sdram->bear; break; case 0x20: /* SDRAM_CFG */ ret = sdram->cfg; break; case 0x24: /* SDRAM_STATUS */ ret = sdram->status; break; case 0x30: /* SDRAM_RTR */ ret = sdram->rtr; break; case 0x34: /* SDRAM_PMIT */ ret = sdram->pmit; break; case 0x40: /* SDRAM_B0CR */ ret = sdram->bcr[0]; break; case 0x44: /* SDRAM_B1CR */ ret = sdram->bcr[1]; break; case 0x48: /* SDRAM_B2CR */ ret = sdram->bcr[2]; break; case 0x4C: /* SDRAM_B3CR */ ret = sdram->bcr[3]; break; case 0x80: /* SDRAM_TR */ ret = -1; /* ? */ break; case 0x94: /* SDRAM_ECCCFG */ ret = sdram->ecccfg; break; case 0x98: /* SDRAM_ECCESR */ ret = sdram->eccesr; break; default: /* Error */ ret = -1; break; } break; default: /* Avoid gcc warning */ break; } return ret;}static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val){ ppc4xx_sdram_t *sdram; sdram = opaque; switch (dcrn) { case SDRAM0_CFGADDR: sdram->addr = val; break; case SDRAM0_CFGDATA: switch (sdram->addr) { case 0x00: /* SDRAM_BESR0 */ sdram->besr0 &= ~val; break; case 0x08: /* SDRAM_BESR1 */ sdram->besr1 &= ~val; break; case 0x10: /* SDRAM_BEAR */ sdram->bear = val; break; case 0x20: /* SDRAM_CFG */ val &= 0xFFE00000; if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) {#ifdef DEBUG_SDRAM printf("%s: enable SDRAM controller\n", __func__);#endif /* validate all RAM mappings */ sdram_map_bcr(sdram); sdram->status &= ~0x80000000; } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) {#ifdef DEBUG_SDRAM printf("%s: disable SDRAM controller\n", __func__);#endif /* invalidate all RAM mappings */ sdram_unmap_bcr(sdram); sdram->status |= 0x80000000; } if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) sdram->status |= 0x40000000; else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) sdram->status &= ~0x40000000; sdram->cfg = val; break; case 0x24: /* SDRAM_STATUS */ /* Read-only register */ break; case 0x30: /* SDRAM_RTR */ sdram->rtr = val & 0x3FF80000; break; case 0x34: /* SDRAM_PMIT */ sdram->pmit = (val & 0xF8000000) | 0x07C00000; break; case 0x40: /* SDRAM_B0CR */ sdram_set_bcr(&sdram->bcr[0], val, sdram->cfg & 0x80000000); break; case 0x44: /* SDRAM_B1CR */ sdram_set_bcr(&sdram->bcr[1], val, sdram->cfg & 0x80000000); break; case 0x48: /* SDRAM_B2CR */ sdram_set_bcr(&sdram->bcr[2], val, sdram->cfg & 0x80000000); break; case 0x4C: /* SDRAM_B3CR */ sdram_set_bcr(&sdram->bcr[3], val, sdram->cfg & 0x80000000); break; case 0x80: /* SDRAM_TR */ sdram->tr = val & 0x018FC01F; break; case 0x94: /* SDRAM_ECCCFG */ sdram->ecccfg = val & 0x00F00000; break; case 0x98: /* SDRAM_ECCESR */ val &= 0xFFF0F000; if (sdram->eccesr == 0 && val != 0) qemu_irq_raise(sdram->irq); else if (sdram->eccesr != 0 && val == 0) qemu_irq_lower(sdram->irq); sdram->eccesr = val; break; default: /* Error */ break; } break; }}static void sdram_reset (void *opaque){ ppc4xx_sdram_t *sdram; sdram = opaque; sdram->addr = 0x00000000; sdram->bear = 0x00000000; sdram->besr0 = 0x00000000; /* No error */ sdram->besr1 = 0x00000000; /* No error */ sdram->cfg = 0x00000000; sdram->ecccfg = 0x00000000; /* No ECC */ sdram->eccesr = 0x00000000; /* No error */ sdram->pmit = 0x07C00000; sdram->rtr = 0x05F00000; sdram->tr = 0x00854009; /* We pre-initialize RAM banks */ sdram->status = 0x00000000; sdram->cfg = 0x00800000; sdram_unmap_bcr(sdram);}void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks, target_phys_addr_t *ram_bases, target_phys_addr_t *ram_sizes, int do_init){ ppc4xx_sdram_t *sdram; sdram = qemu_mallocz(sizeof(ppc4xx_sdram_t)); if (sdram != NULL) { sdram->irq = irq; sdram->nbanks = nbanks; memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t)); memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t)); sdram_reset(sdram); qemu_register_reset(&sdram_reset, sdram); ppc_dcr_register(env, SDRAM0_CFGADDR, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); if (do_init) sdram_map_bcr(sdram); }}/*****************************************************************************//* Peripheral controller */typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;struct ppc4xx_ebc_t { uint32_t addr; uint32_t bcr[8]; uint32_t bap[8]; uint32_t bear; uint32_t besr0; uint32_t besr1; uint32_t cfg;};enum { EBC0_CFGADDR = 0x012, EBC0_CFGDATA = 0x013,};static target_ulong dcr_read_ebc (void *opaque, int dcrn){ ppc4xx_ebc_t *ebc; target_ulong ret; ebc = opaque; switch (dcrn) { case EBC0_CFGADDR: ret = ebc->addr; break; case EBC0_CFGDATA: switch (ebc->addr) { case 0x00: /* B0CR */ ret = ebc->bcr[0]; break; case 0x01: /* B1CR */ ret = ebc->bcr[1]; break; case 0x02: /* B2CR */ ret = ebc->bcr[2]; break; case 0x03: /* B3CR */ ret = ebc->bcr[3]; break; case 0x04: /* B4CR */ ret = ebc->bcr[4]; break; case 0x05: /* B5CR */ ret = ebc->bcr[5]; break; case 0x06: /* B6CR */ ret = ebc->bcr[6]; break; case 0x07: /* B7CR */ ret = ebc->bcr[7]; break; case 0x10: /* B0AP */ ret = ebc->bap[0]; break; case 0x11: /* B1AP */ ret = ebc->bap[1]; break; case 0x12: /* B2AP */ ret = ebc->bap[2]; break; case 0x13: /* B3AP */ ret = ebc->bap[3]; break; case 0x14: /* B4AP */ ret = ebc->bap[4]; break; case 0x15: /* B5AP */ ret = ebc->bap[5]; break; case 0x16: /* B6AP */ ret = ebc->bap[6]; break; case 0x17: /* B7AP */ ret = ebc->bap[7]; break; case 0x20: /* BEAR */ ret = ebc->bear; break; case 0x21: /* BESR0 */ ret = ebc->besr0; break; case 0x22: /* BESR1 */ ret = ebc->besr1; break; case 0x23: /* CFG */ ret = ebc->cfg; break; default: ret = 0x00000000; break; } default: ret = 0x00000000; break; } return ret;}static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val){ ppc4xx_ebc_t *ebc; ebc = opaque; switch (dcrn) { case EBC0_CFGADDR: ebc->addr = val; break; case EBC0_CFGDATA: switch (ebc->addr) { case 0x00: /* B0CR */ break; case 0x01: /* B1CR */ break; case 0x02: /* B2CR */ break; case 0x03: /* B3CR */ break; case 0x04: /* B4CR */ break; case 0x05: /* B5CR */ break; case 0x06: /* B6CR */ break; case 0x07: /* B7CR */ break; case 0x10: /* B0AP */ break; case 0x11: /* B1AP */ break; case 0x12: /* B2AP */ break; case 0x13: /* B3AP */ break; case 0x14: /* B4AP */ break; case 0x15: /* B5AP */ break; case 0x16: /* B6AP */ break; case 0x17: /* B7AP */ break; case 0x20: /* BEAR */ break; case 0x21: /* BESR0 */ break; case 0x22: /* BESR1 */ break; case 0x23: /* CFG */ break; default: break; } break; default: break; }}static void ebc_reset (void *opaque){ ppc4xx_ebc_t *ebc; int i; ebc = opaque; ebc->addr = 0x00000000; ebc->bap[0] = 0x7F8FFE80; ebc->bcr[0] = 0xFFE28000; for (i = 0; i < 8; i++) { ebc->bap[i] = 0x00000000; ebc->bcr[i] = 0x00000000; } ebc->besr0 = 0x00000000; ebc->besr1 = 0x00000000; ebc->cfg = 0x80400000;}void ppc405_ebc_init (CPUState *env){ ppc4xx_ebc_t *ebc; ebc = qemu_mallocz(sizeof(ppc4xx_ebc_t)); if (ebc != NULL) { ebc_reset(ebc); qemu_register_reset(&ebc_reset, ebc); ppc_dcr_register(env, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); ppc_dcr_register(env, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); }}/*****************************************************************************//* DMA controller */enum { DMA0_CR0 = 0x100, DMA0_CT0 = 0x101, DMA0_DA0 = 0x102, DMA0_SA0 = 0x103, DMA0_SG0 = 0x104, DMA0_CR1 = 0x108, DMA0_CT1 = 0x109, DMA0_DA1 = 0x10A, DMA0_SA1 = 0x10B, DMA0_SG1 = 0x10C, DMA0_CR2 = 0x110, DMA0_CT2 = 0x111, DMA0_DA2 = 0x112, DMA0_SA2 = 0x113, DMA0_SG2 = 0x114, DMA0_CR3 = 0x118, DMA0_CT3 = 0x119, DMA0_DA3 = 0x11A, DMA0_SA3 = 0x11B, DMA0_SG3 = 0x11C, DMA0_SR = 0x120, DMA0_SGC = 0x123, DMA0_SLP = 0x125, DMA0_POL = 0x126,};typedef struct ppc405_dma_t ppc405_dma_t;struct ppc405_dma_t { qemu_irq irqs[4]; uint32_t cr[4]; uint32_t ct[4]; uint32_t da[4]; uint32_t sa[4]; uint32_t sg[4]; uint32_t sr; uint32_t sgc; uint32_t slp; uint32_t pol;};static target_ulong dcr_read_dma (void *opaque, int dcrn){ ppc405_dma_t *dma; dma = opaque; return 0;}static void dcr_write_dma (void *opaque, int dcrn, target_ulong val){ ppc405_dma_t *dma; dma = opaque;}static void ppc405_dma_reset (void *opaque){ ppc405_dma_t *dma; int i; dma = opaque; for (i = 0; i < 4; i++) { dma->cr[i] = 0x00000000; dma->ct[i] = 0x00000000; dma->da[i] = 0x00000000; dma->sa[i] = 0x00000000; dma->sg[i] = 0x00000000; }?? 快捷鍵說明
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