dma->sr = 0x00000000;    dma->sgc = 0x00000000;    dma->slp = 0x7C000000;    dma->pol = 0x00000000;}void ppc405_dma_init (CPUState *env, qemu_irq irqs[4]){    ppc405_dma_t *dma;    dma = qemu_mallocz(sizeof(ppc405_dma_t));    if (dma != NULL) {        memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));        ppc405_dma_reset(dma);        qemu_register_reset(&ppc405_dma_reset, dma);        ppc_dcr_register(env, DMA0_CR0,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CT0,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_DA0,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SA0,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SG0,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CR1,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CT1,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_DA1,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SA1,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SG1,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CR2,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CT2,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_DA2,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SA2,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SG2,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CR3,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_CT3,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_DA3,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SA3,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SG3,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SR,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SGC,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_SLP,                         dma, &dcr_read_dma, &dcr_write_dma);        ppc_dcr_register(env, DMA0_POL,                         dma, &dcr_read_dma, &dcr_write_dma);    }}/*****************************************************************************//* GPIO */typedef struct ppc405_gpio_t ppc405_gpio_t;struct ppc405_gpio_t {    target_phys_addr_t base;    uint32_t or;    uint32_t tcr;    uint32_t osrh;    uint32_t osrl;    uint32_t tsrh;    uint32_t tsrl;    uint32_t odr;    uint32_t ir;    uint32_t rr1;    uint32_t isr1h;    uint32_t isr1l;};static uint32_t ppc405_gpio_readb (void *opaque, target_phys_addr_t addr){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX "\n", __func__, addr);#endif    return 0;}static void ppc405_gpio_writeb (void *opaque,                                target_phys_addr_t addr, uint32_t value){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);#endif}static uint32_t ppc405_gpio_readw (void *opaque, target_phys_addr_t addr){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX "\n", __func__, addr);#endif    return 0;}static void ppc405_gpio_writew (void *opaque,                                target_phys_addr_t addr, uint32_t value){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);#endif}static uint32_t ppc405_gpio_readl (void *opaque, target_phys_addr_t addr){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX "\n", __func__, addr);#endif    return 0;}static void ppc405_gpio_writel (void *opaque,                                target_phys_addr_t addr, uint32_t value){    ppc405_gpio_t *gpio;    gpio = opaque;#ifdef DEBUG_GPIO    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);#endif}static CPUReadMemoryFunc *ppc405_gpio_read[] = {    &ppc405_gpio_readb,    &ppc405_gpio_readw,    &ppc405_gpio_readl,};static CPUWriteMemoryFunc *ppc405_gpio_write[] = {    &ppc405_gpio_writeb,    &ppc405_gpio_writew,    &ppc405_gpio_writel,};static void ppc405_gpio_reset (void *opaque){    ppc405_gpio_t *gpio;    gpio = opaque;}void ppc405_gpio_init (CPUState *env, ppc4xx_mmio_t *mmio,                       target_phys_addr_t offset){    ppc405_gpio_t *gpio;    gpio = qemu_mallocz(sizeof(ppc405_gpio_t));    if (gpio != NULL) {        gpio->base = offset;        ppc405_gpio_reset(gpio);        qemu_register_reset(&ppc405_gpio_reset, gpio);#ifdef DEBUG_GPIO        printf("%s: offset " PADDRX "\n", __func__, offset);#endif        ppc4xx_mmio_register(env, mmio, offset, 0x038,                             ppc405_gpio_read, ppc405_gpio_write, gpio);    }}/*****************************************************************************//* Serial ports */static CPUReadMemoryFunc *serial_mm_read[] = {    &serial_mm_readb,    &serial_mm_readw,    &serial_mm_readl,};static CPUWriteMemoryFunc *serial_mm_write[] = {    &serial_mm_writeb,    &serial_mm_writew,    &serial_mm_writel,};void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,                         target_phys_addr_t offset, qemu_irq irq,                         CharDriverState *chr){    void *serial;#ifdef DEBUG_SERIAL    printf("%s: offset " PADDRX "\n", __func__, offset);#endif    serial = serial_mm_init(offset, 0, irq, chr, 0);    ppc4xx_mmio_register(env, mmio, offset, 0x008,                         serial_mm_read, serial_mm_write, serial);}/*****************************************************************************//* On Chip Memory */enum {    OCM0_ISARC   = 0x018,    OCM0_ISACNTL = 0x019,    OCM0_DSARC   = 0x01A,    OCM0_DSACNTL = 0x01B,};typedef struct ppc405_ocm_t ppc405_ocm_t;struct ppc405_ocm_t {    target_ulong offset;    uint32_t isarc;    uint32_t isacntl;    uint32_t dsarc;    uint32_t dsacntl;};static void ocm_update_mappings (ppc405_ocm_t *ocm,                                 uint32_t isarc, uint32_t isacntl,                                 uint32_t dsarc, uint32_t dsacntl){#ifdef DEBUG_OCM    printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32           " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32           " (%08" PRIx32 " %08" PRIx32 ")\n",           isarc, isacntl, dsarc, dsacntl,           ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);#endif    if (ocm->isarc != isarc ||        (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {        if (ocm->isacntl & 0x80000000) {            /* Unmap previously assigned memory region */            printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);            cpu_register_physical_memory(ocm->isarc, 0x04000000,                                         IO_MEM_UNASSIGNED);        }        if (isacntl & 0x80000000) {            /* Map new instruction memory region */#ifdef DEBUG_OCM            printf("OCM map ISA %08" PRIx32 "\n", isarc);#endif            cpu_register_physical_memory(isarc, 0x04000000,                                         ocm->offset | IO_MEM_RAM);        }    }    if (ocm->dsarc != dsarc ||        (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {        if (ocm->dsacntl & 0x80000000) {            /* Beware not to unmap the region we just mapped */            if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {                /* Unmap previously assigned memory region */#ifdef DEBUG_OCM                printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);#endif                cpu_register_physical_memory(ocm->dsarc, 0x04000000,                                             IO_MEM_UNASSIGNED);            }        }        if (dsacntl & 0x80000000) {            /* Beware not to remap the region we just mapped */            if (!(isacntl & 0x80000000) || dsarc != isarc) {                /* Map new data memory region */#ifdef DEBUG_OCM                printf("OCM map DSA %08" PRIx32 "\n", dsarc);#endif                cpu_register_physical_memory(dsarc, 0x04000000,                                             ocm->offset | IO_MEM_RAM);            }        }    }}static target_ulong dcr_read_ocm (void *opaque, int dcrn){    ppc405_ocm_t *ocm;    target_ulong ret;    ocm = opaque;    switch (dcrn) {    case OCM0_ISARC:        ret = ocm->isarc;        break;    case OCM0_ISACNTL:        ret = ocm->isacntl;        break;    case OCM0_DSARC:        ret = ocm->dsarc;        break;    case OCM0_DSACNTL:        ret = ocm->dsacntl;        break;    default:        ret = 0;        break;    }    return ret;}static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val){    ppc405_ocm_t *ocm;    uint32_t isarc, dsarc, isacntl, dsacntl;    ocm = opaque;    isarc = ocm->isarc;    dsarc = ocm->dsarc;    isacntl = ocm->isacntl;    dsacntl = ocm->dsacntl;    switch (dcrn) {    case OCM0_ISARC:        isarc = val & 0xFC000000;        break;    case OCM0_ISACNTL:        isacntl = val & 0xC0000000;        break;    case OCM0_DSARC:        isarc = val & 0xFC000000;        break;    case OCM0_DSACNTL:        isacntl = val & 0xC0000000;        break;    }    ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);    ocm->isarc = isarc;    ocm->dsarc = dsarc;    ocm->isacntl = isacntl;    ocm->dsacntl = dsacntl;}static void ocm_reset (void *opaque){    ppc405_ocm_t *ocm;    uint32_t isarc, dsarc, isacntl, dsacntl;    ocm = opaque;    isarc = 0x00000000;    isacntl = 0x00000000;    dsarc = 0x00000000;    dsacntl = 0x00000000;    ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);    ocm->isarc = isarc;    ocm->dsarc = dsarc;    ocm->isacntl = isacntl;    ocm->dsacntl = dsacntl;}void ppc405_ocm_init (CPUState *env, unsigned long offset){    ppc405_ocm_t *ocm;    ocm = qemu_mallocz(sizeof(ppc405_ocm_t));    if (ocm != NULL) {        ocm->offset = offset;        ocm_reset(ocm);        qemu_register_reset(&ocm_reset, ocm);        ppc_dcr_register(env, OCM0_ISARC,                         ocm, &dcr_read_ocm, &dcr_write_ocm);        ppc_dcr_register(env, OCM0_ISACNTL,                         ocm, &dcr_read_ocm, &dcr_write_ocm);        ppc_dcr_register(env, OCM0_DSARC,                         ocm, &dcr_read_ocm, &dcr_write_ocm);        ppc_dcr_register(env, OCM0_DSACNTL,                         ocm, &dcr_read_ocm, &dcr_write_ocm);    }}/*****************************************************************************//* I2C controller */typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;struct ppc4xx_i2c_t {    target_phys_addr_t base;    qemu_irq irq;    uint8_t mdata;    uint8_t lmadr;    uint8_t hmadr;    uint8_t cntl;    uint8_t mdcntl;    uint8_t sts;    uint8_t extsts;    uint8_t sdata;    uint8_t lsadr;    uint8_t hsadr;    uint8_t clkdiv;    uint8_t intrmsk;    uint8_t xfrcnt;    uint8_t xtcntlss;    uint8_t directcntl;};static uint32_t ppc4xx_i2c_readb (void *opaque, target_phys_addr_t addr){    ppc4xx_i2c_t *i2c;    uint32_t ret;#ifdef DEBUG_I2C    printf("%s: addr " PADDRX "\n", __func__, addr);#endif    i2c = opaque;    switch (addr - i2c->base) {    case 0x00:        //        i2c_readbyte(&i2c->mdata);        ret = i2c->mdata;        break;    case 0x02:        ret = i2c->sdata;        break;    case 0x04:        ret = i2c->lmadr;        break;    case 0x05:        ret = i2c->hmadr;        break;    case 0x06:        ret = i2c->cntl;        break;    case 0x07:        ret = i2c->mdcntl;        break;    case 0x08:        ret = i2c->sts;        break;    case 0x09:        ret = i2c->extsts;        break;    case 0x0A:        ret = i2c->lsadr;        break;    case 0x0B:        ret = i2c->hsadr;        break;    case 0x0C:        ret = i2c->clkdiv;        break;    case 0x0D:        ret = i2c->intrmsk;        break;    case 0x0E:        ret = i2c->xfrcnt;        break;    case 0x0F:        ret = i2c->xtcntlss;        break;    case 0x10:        ret = i2c->directcntl;        break;    default:        ret = 0x00;        break;    }#ifdef DEBUG_I2C    printf("%s: addr " PADDRX " %02" PRIx32 "\n", __func__, addr, ret);#endif    return ret;}static void ppc4xx_i2c_writeb (void *opaque,                               target_phys_addr_t addr, uint32_t value){    ppc4xx_i2c_t *i2c;#ifdef DEBUG_I2C    printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value);#endif    i2c = opaque;    switch (addr - i2c->base) {    case 0x00:        i2c->mdata = value;        //        i2c_sendbyte(&i2c->mdata);        break;    case 0x02:        i2c->sdata = value;        break;    case 0x04:        i2c->lmadr = value;        break;    case 0x05:        i2c->hmadr = value;        break;    case 0x06:        i2c->cntl = value;        break;    case 0x07:        i2c->mdcntl = value & 0xDF;        break;    case 0x08: