# define OMAP_DMA_UART1_RX		13# define OMAP_DMA_UART2_TX		14# define OMAP_DMA_UART2_RX		15# define OMAP_DMA_MCBSP2_TX		16# define OMAP_DMA_MCBSP2_RX		17# define OMAP_DMA_UART3_TX		18# define OMAP_DMA_UART3_RX		19# define OMAP_DMA_CAMERA_IF_RX		20# define OMAP_DMA_MMC_TX		21# define OMAP_DMA_MMC_RX		22# define OMAP_DMA_NAND			23	/* Not in OMAP310 */# define OMAP_DMA_IRQ_LCD_LINE		24	/* Not in OMAP310 */# define OMAP_DMA_MEMORY_STICK		25	/* Not in OMAP310 */# define OMAP_DMA_USB_W2FC_RX0		26# define OMAP_DMA_USB_W2FC_RX1		27# define OMAP_DMA_USB_W2FC_RX2		28# define OMAP_DMA_USB_W2FC_TX0		29# define OMAP_DMA_USB_W2FC_TX1		30# define OMAP_DMA_USB_W2FC_TX2		31/* These are only for 1610 */# define OMAP_DMA_CRYPTO_DES_IN		32# define OMAP_DMA_SPI_TX		33# define OMAP_DMA_SPI_RX		34# define OMAP_DMA_CRYPTO_HASH		35# define OMAP_DMA_CCP_ATTN		36# define OMAP_DMA_CCP_FIFO_NOT_EMPTY	37# define OMAP_DMA_CMT_APE_TX_CHAN_0	38# define OMAP_DMA_CMT_APE_RV_CHAN_0	39# define OMAP_DMA_CMT_APE_TX_CHAN_1	40# define OMAP_DMA_CMT_APE_RV_CHAN_1	41# define OMAP_DMA_CMT_APE_TX_CHAN_2	42# define OMAP_DMA_CMT_APE_RV_CHAN_2	43# define OMAP_DMA_CMT_APE_TX_CHAN_3	44# define OMAP_DMA_CMT_APE_RV_CHAN_3	45# define OMAP_DMA_CMT_APE_TX_CHAN_4	46# define OMAP_DMA_CMT_APE_RV_CHAN_4	47# define OMAP_DMA_CMT_APE_TX_CHAN_5	48# define OMAP_DMA_CMT_APE_RV_CHAN_5	49# define OMAP_DMA_CMT_APE_TX_CHAN_6	50# define OMAP_DMA_CMT_APE_RV_CHAN_6	51# define OMAP_DMA_CMT_APE_TX_CHAN_7	52# define OMAP_DMA_CMT_APE_RV_CHAN_7	53# define OMAP_DMA_MMC2_TX		54# define OMAP_DMA_MMC2_RX		55# define OMAP_DMA_CRYPTO_DES_OUT	56struct omap_mpu_timer_s;struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,                qemu_irq irq, omap_clk clk);struct omap_watchdog_timer_s;struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,                qemu_irq irq, omap_clk clk);struct omap_32khz_timer_s;struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,                qemu_irq irq, omap_clk clk);struct omap_tipb_bridge_s;struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,                qemu_irq abort_irq, omap_clk clk);struct omap_uart_s;struct omap_uart_s *omap_uart_init(target_phys_addr_t base,                qemu_irq irq, omap_clk clk, CharDriverState *chr);struct omap_mpuio_s;struct omap_mpuio_s *omap_mpuio_init(target_phys_addr_t base,                qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,                omap_clk clk);qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s);void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler);void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down);struct omap_gpio_s;struct omap_gpio_s *omap_gpio_init(target_phys_addr_t base,                qemu_irq irq, omap_clk clk);qemu_irq *omap_gpio_in_get(struct omap_gpio_s *s);void omap_gpio_out_set(struct omap_gpio_s *s, int line, qemu_irq handler);struct uwire_slave_s {    uint16_t (*receive)(void *opaque);    void (*send)(void *opaque, uint16_t data);    void *opaque;};struct omap_uwire_s;struct omap_uwire_s *omap_uwire_init(target_phys_addr_t base,                qemu_irq *irq, qemu_irq dma, omap_clk clk);void omap_uwire_attach(struct omap_uwire_s *s,                struct uwire_slave_s *slave, int chipselect);struct omap_rtc_s;struct omap_rtc_s *omap_rtc_init(target_phys_addr_t base,                qemu_irq *irq, omap_clk clk);struct i2s_codec_s {    void *opaque;    /* The CPU can call this if it is generating the clock signal on the     * i2s port.  The CODEC can ignore it if it is set up as a clock     * master and generates its own clock.  */    void (*set_rate)(void *opaque, int in, int out);    void (*tx_swallow)(void *opaque);    qemu_irq rx_swallow;    qemu_irq tx_start;    int tx_rate;    int cts;    int rx_rate;    int rts;    struct i2s_fifo_s {        uint8_t *fifo;        int len;        int start;        int size;    } in, out;};struct omap_mcbsp_s;struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,                qemu_irq *irq, qemu_irq *dma, omap_clk clk);void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, struct i2s_codec_s *slave);struct omap_lpg_s;struct omap_lpg_s *omap_lpg_init(target_phys_addr_t base, omap_clk clk);/* omap_lcdc.c */struct omap_lcd_panel_s;void omap_lcdc_reset(struct omap_lcd_panel_s *s);struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,                struct omap_dma_lcd_channel_s *dma, DisplayState *ds,                ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);/* omap_mmc.c */struct omap_mmc_s;struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,                BlockDriverState *bd,                qemu_irq irq, qemu_irq dma[], omap_clk clk);void omap_mmc_reset(struct omap_mmc_s *s);void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);/* omap_i2c.c */struct omap_i2c_s;struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,                qemu_irq irq, qemu_irq *dma, omap_clk clk);void omap_i2c_reset(struct omap_i2c_s *s);i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);# define cpu_is_omap310(cpu)		(cpu->mpu_model == omap310)# define cpu_is_omap1510(cpu)		(cpu->mpu_model == omap1510)# define cpu_is_omap15xx(cpu)		\        (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))# define cpu_class_omap1(cpu)		1struct omap_mpu_state_s {    enum omap1_mpu_model {        omap310,        omap1510,    } mpu_model;    CPUState *env;    qemu_irq *irq[2];    qemu_irq *drq;    qemu_irq wakeup;    struct omap_dma_port_if_s {        uint32_t (*read[3])(struct omap_mpu_state_s *s,                        target_phys_addr_t offset);        void (*write[3])(struct omap_mpu_state_s *s,                        target_phys_addr_t offset, uint32_t value);        int (*addr_valid)(struct omap_mpu_state_s *s,                        target_phys_addr_t addr);    } port[omap_dma_port_last];    unsigned long sdram_size;    unsigned long sram_size;    /* MPUI-TIPB peripherals */    struct omap_uart_s *uart[3];    struct omap_gpio_s *gpio;    struct omap_mcbsp_s *mcbsp1;    struct omap_mcbsp_s *mcbsp3;    /* MPU public TIPB peripherals */    struct omap_32khz_timer_s *os_timer;    struct omap_mmc_s *mmc;    struct omap_mpuio_s *mpuio;    struct omap_uwire_s *microwire;    struct {        uint8_t output;        uint8_t level;        uint8_t enable;        int clk;    } pwl;    struct {        uint8_t frc;        uint8_t vrc;        uint8_t gcr;        omap_clk clk;    } pwt;    struct omap_i2c_s *i2c;    struct omap_rtc_s *rtc;    struct omap_mcbsp_s *mcbsp2;    struct omap_lpg_s *led[2];    /* MPU private TIPB peripherals */    struct omap_intr_handler_s *ih[2];    struct omap_dma_s *dma;    struct omap_mpu_timer_s *timer[3];    struct omap_watchdog_timer_s *wdt;    struct omap_lcd_panel_s *lcd;    target_phys_addr_t ulpd_pm_base;    uint32_t ulpd_pm_regs[21];    int64_t ulpd_gauge_start;    target_phys_addr_t pin_cfg_base;    uint32_t func_mux_ctrl[14];    uint32_t comp_mode_ctrl[1];    uint32_t pull_dwn_ctrl[4];    uint32_t gate_inh_ctrl[1];    uint32_t voltage_ctrl[1];    uint32_t test_dbg_ctrl[1];    uint32_t mod_conf_ctrl[1];    int compat1509;    uint32_t mpui_ctrl;    target_phys_addr_t mpui_base;    struct omap_tipb_bridge_s *private_tipb;    struct omap_tipb_bridge_s *public_tipb;    target_phys_addr_t tcmi_base;    uint32_t tcmi_regs[17];    struct dpll_ctl_s {        target_phys_addr_t base;        uint16_t mode;        omap_clk dpll;    } dpll[3];    omap_clk clks;    struct {        target_phys_addr_t mpu_base;        target_phys_addr_t dsp_base;        int cold_start;        int clocking_scheme;        uint16_t arm_ckctl;        uint16_t arm_idlect1;        uint16_t arm_idlect2;        uint16_t arm_ewupct;        uint16_t arm_rstct1;        uint16_t arm_rstct2;        uint16_t arm_ckout1;        int dpll1_mode;        uint16_t dsp_idlect1;        uint16_t dsp_idlect2;        uint16_t dsp_rstct2;    } clkm;} *omap310_mpu_init(unsigned long sdram_size,                DisplayState *ds, const char *core);# if TARGET_PHYS_ADDR_BITS == 32#  define OMAP_FMT_plx "%#08x"# elif TARGET_PHYS_ADDR_BITS == 64#  define OMAP_FMT_plx "%#08" PRIx64# else#  error TARGET_PHYS_ADDR_BITS undefined# endifuint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr);void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,                uint32_t value);uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr);void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,                uint32_t value);uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,                uint32_t value);# define OMAP_BAD_REG(paddr)		\        printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)# define OMAP_RO_REG(paddr)		\        printf("%s: Read-only register " OMAP_FMT_plx "\n",	\                        __FUNCTION__, paddr)# define TCMI_VERBOSE			1//# define MEM_VERBOSE			1# ifdef TCMI_VERBOSE#  define OMAP_8B_REG(paddr)		\        printf("%s: 8-bit register " OMAP_FMT_plx "\n",	\                        __FUNCTION__, paddr)#  define OMAP_16B_REG(paddr)		\        printf("%s: 16-bit register " OMAP_FMT_plx "\n",	\                        __FUNCTION__, paddr)#  define OMAP_32B_REG(paddr)		\        printf("%s: 32-bit register " OMAP_FMT_plx "\n",	\                        __FUNCTION__, paddr)# else#  define OMAP_8B_REG(paddr)#  define OMAP_16B_REG(paddr)#  define OMAP_32B_REG(paddr)# endif# define OMAP_MPUI_REG_MASK		0x000007ff# ifdef MEM_VERBOSEstruct io_fn {    CPUReadMemoryFunc **mem_read;    CPUWriteMemoryFunc **mem_write;    void *opaque;    int in;};static uint32_t io_readb(void *opaque, target_phys_addr_t addr){    struct io_fn *s = opaque;    uint32_t ret;    s->in ++;    ret = s->mem_read[0](s->opaque, addr);    s->in --;    if (!s->in)        fprintf(stderr, "%08x ---> %02x\n", (uint32_t) addr, ret);    return ret;}static uint32_t io_readh(void *opaque, target_phys_addr_t addr){    struct io_fn *s = opaque;    uint32_t ret;    s->in ++;    ret = s->mem_read[1](s->opaque, addr);    s->in --;    if (!s->in)        fprintf(stderr, "%08x ---> %04x\n", (uint32_t) addr, ret);    return ret;}static uint32_t io_readw(void *opaque, target_phys_addr_t addr){    struct io_fn *s = opaque;    uint32_t ret;    s->in ++;    ret = s->mem_read[2](s->opaque, addr);    s->in --;    if (!s->in)        fprintf(stderr, "%08x ---> %08x\n", (uint32_t) addr, ret);    return ret;}static void io_writeb(void *opaque, target_phys_addr_t addr, uint32_t value){    struct io_fn *s = opaque;    if (!s->in)        fprintf(stderr, "%08x <--- %02x\n", (uint32_t) addr, value);    s->in ++;    s->mem_write[0](s->opaque, addr, value);    s->in --;}static void io_writeh(void *opaque, target_phys_addr_t addr, uint32_t value){    struct io_fn *s = opaque;    if (!s->in)        fprintf(stderr, "%08x <--- %04x\n", (uint32_t) addr, value);    s->in ++;    s->mem_write[1](s->opaque, addr, value);    s->in --;}static void io_writew(void *opaque, target_phys_addr_t addr, uint32_t value){    struct io_fn *s = opaque;    if (!s->in)        fprintf(stderr, "%08x <--- %08x\n", (uint32_t) addr, value);    s->in ++;    s->mem_write[2](s->opaque, addr, value);    s->in --;}static CPUReadMemoryFunc *io_readfn[] = { io_readb, io_readh, io_readw, };static CPUWriteMemoryFunc *io_writefn[] = { io_writeb, io_writeh, io_writew, };inline static int debug_register_io_memory(int io_index,                CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write,                void *opaque){    struct io_fn *s = qemu_malloc(sizeof(struct io_fn));    s->mem_read = mem_read;    s->mem_write = mem_write;    s->opaque = opaque;    s->in = 0;    return cpu_register_io_memory(io_index, io_readfn, io_writefn, s);}#  define cpu_register_io_memory	debug_register_io_memory# endif/* Not really omap specific, but is the only thing that uses the   uwire interface.  *//* tsc210x.c */struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip);#endif /* hw_omap_h */