} else {    no_timer:        qemu_del_timer(s->timer);    }}static void apic_timer(void *opaque){    APICState *s = opaque;    if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {        apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);    }    apic_timer_update(s, s->next_time);}static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr){    return 0;}static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr){    return 0;}static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val){}static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val){}static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr){    CPUState *env;    APICState *s;    uint32_t val;    int index;    env = cpu_single_env;    if (!env)        return 0;    s = env->apic_state;    index = (addr >> 4) & 0xff;    switch(index) {    case 0x02: /* id */        val = s->id << 24;        break;    case 0x03: /* version */        val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */        break;    case 0x08:        val = s->tpr;        break;    case 0x09:        val = apic_get_arb_pri(s);        break;    case 0x0a:        /* ppr */        val = apic_get_ppr(s);        break;    case 0x0d:        val = s->log_dest << 24;        break;    case 0x0e:        val = s->dest_mode << 28;        break;    case 0x0f:        val = s->spurious_vec;        break;    case 0x10 ... 0x17:        val = s->isr[index & 7];        break;    case 0x18 ... 0x1f:        val = s->tmr[index & 7];        break;    case 0x20 ... 0x27:        val = s->irr[index & 7];        break;    case 0x28:        val = s->esr;        break;    case 0x30:    case 0x31:        val = s->icr[index & 1];        break;    case 0x32 ... 0x37:        val = s->lvt[index - 0x32];        break;    case 0x38:        val = s->initial_count;        break;    case 0x39:        val = apic_get_current_count(s);        break;    case 0x3e:        val = s->divide_conf;        break;    default:        s->esr |= ESR_ILLEGAL_ADDRESS;        val = 0;        break;    }#ifdef DEBUG_APIC    printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);#endif    return val;}static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val){    CPUState *env;    APICState *s;    int index;    env = cpu_single_env;    if (!env)        return;    s = env->apic_state;#ifdef DEBUG_APIC    printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);#endif    index = (addr >> 4) & 0xff;    switch(index) {    case 0x02:        s->id = (val >> 24);        break;    case 0x03:        break;    case 0x08:        s->tpr = val;        apic_update_irq(s);        break;    case 0x09:    case 0x0a:        break;    case 0x0b: /* EOI */        apic_eoi(s);        break;    case 0x0d:        s->log_dest = val >> 24;        break;    case 0x0e:        s->dest_mode = val >> 28;        break;    case 0x0f:        s->spurious_vec = val & 0x1ff;        apic_update_irq(s);        break;    case 0x10 ... 0x17:    case 0x18 ... 0x1f:    case 0x20 ... 0x27:    case 0x28:        break;    case 0x30:        s->icr[0] = val;        apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,                     (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),                     (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);        break;    case 0x31:        s->icr[1] = val;        break;    case 0x32 ... 0x37:        {            int n = index - 0x32;            s->lvt[n] = val;            if (n == APIC_LVT_TIMER)                apic_timer_update(s, qemu_get_clock(vm_clock));        }        break;    case 0x38:        s->initial_count = val;        s->initial_count_load_time = qemu_get_clock(vm_clock);        apic_timer_update(s, s->initial_count_load_time);        break;    case 0x39:        break;    case 0x3e:        {            int v;            s->divide_conf = val & 0xb;            v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);            s->count_shift = (v + 1) & 7;        }        break;    default:        s->esr |= ESR_ILLEGAL_ADDRESS;        break;    }}static void apic_save(QEMUFile *f, void *opaque){    APICState *s = opaque;    int i;    qemu_put_be32s(f, &s->apicbase);    qemu_put_8s(f, &s->id);    qemu_put_8s(f, &s->arb_id);    qemu_put_8s(f, &s->tpr);    qemu_put_be32s(f, &s->spurious_vec);    qemu_put_8s(f, &s->log_dest);    qemu_put_8s(f, &s->dest_mode);    for (i = 0; i < 8; i++) {        qemu_put_be32s(f, &s->isr[i]);        qemu_put_be32s(f, &s->tmr[i]);        qemu_put_be32s(f, &s->irr[i]);    }    for (i = 0; i < APIC_LVT_NB; i++) {        qemu_put_be32s(f, &s->lvt[i]);    }    qemu_put_be32s(f, &s->esr);    qemu_put_be32s(f, &s->icr[0]);    qemu_put_be32s(f, &s->icr[1]);    qemu_put_be32s(f, &s->divide_conf);    qemu_put_be32(f, s->count_shift);    qemu_put_be32s(f, &s->initial_count);    qemu_put_be64(f, s->initial_count_load_time);    qemu_put_be64(f, s->next_time);    qemu_put_timer(f, s->timer);}static int apic_load(QEMUFile *f, void *opaque, int version_id){    APICState *s = opaque;    int i;    if (version_id > 2)        return -EINVAL;    /* XXX: what if the base changes? (registered memory regions) */    qemu_get_be32s(f, &s->apicbase);    qemu_get_8s(f, &s->id);    qemu_get_8s(f, &s->arb_id);    qemu_get_8s(f, &s->tpr);    qemu_get_be32s(f, &s->spurious_vec);    qemu_get_8s(f, &s->log_dest);    qemu_get_8s(f, &s->dest_mode);    for (i = 0; i < 8; i++) {        qemu_get_be32s(f, &s->isr[i]);        qemu_get_be32s(f, &s->tmr[i]);        qemu_get_be32s(f, &s->irr[i]);    }    for (i = 0; i < APIC_LVT_NB; i++) {        qemu_get_be32s(f, &s->lvt[i]);    }    qemu_get_be32s(f, &s->esr);    qemu_get_be32s(f, &s->icr[0]);    qemu_get_be32s(f, &s->icr[1]);    qemu_get_be32s(f, &s->divide_conf);    s->count_shift=qemu_get_be32(f);    qemu_get_be32s(f, &s->initial_count);    s->initial_count_load_time=qemu_get_be64(f);    s->next_time=qemu_get_be64(f);    if (version_id >= 2)        qemu_get_timer(f, s->timer);    return 0;}static void apic_reset(void *opaque){    APICState *s = opaque;    apic_init_ipi(s);    /*     * LINT0 delivery mode is set to ExtInt at initialization time     * typically by BIOS, so PIC interrupt can be delivered to the     * processor when local APIC is enabled.     */    s->lvt[APIC_LVT_LINT0] = 0x700;}static CPUReadMemoryFunc *apic_mem_read[3] = {    apic_mem_readb,    apic_mem_readw,    apic_mem_readl,};static CPUWriteMemoryFunc *apic_mem_write[3] = {    apic_mem_writeb,    apic_mem_writew,    apic_mem_writel,};int apic_init(CPUState *env){    APICState *s;    if (last_apic_id >= MAX_APICS)        return -1;    s = qemu_mallocz(sizeof(APICState));    if (!s)        return -1;    env->apic_state = s;    apic_init_ipi(s);    s->id = last_apic_id++;    env->cpuid_apic_id = s->id;    s->cpu_env = env;    s->apicbase = 0xfee00000 |        (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;    /*     * LINT0 delivery mode is set to ExtInt at initialization time     * typically by BIOS, so PIC interrupt can be delivered to the     * processor when local APIC is enabled.     */    s->lvt[APIC_LVT_LINT0] = 0x700;    /* XXX: mapping more APICs at the same memory location */    if (apic_io_memory == 0) {        /* NOTE: the APIC is directly connected to the CPU - it is not           on the global memory bus. */        apic_io_memory = cpu_register_io_memory(0, apic_mem_read,                                                apic_mem_write, NULL);        cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,                                     apic_io_memory);    }    s->timer = qemu_new_timer(vm_clock, apic_timer, s);    register_savevm("apic", s->id, 2, apic_save, apic_load, s);    qemu_register_reset(apic_reset, s);    local_apics[s->id] = s;    return 0;}static void ioapic_service(IOAPICState *s){    uint8_t i;    uint8_t trig_mode;    uint8_t vector;    uint8_t delivery_mode;    uint32_t mask;    uint64_t entry;    uint8_t dest;    uint8_t dest_mode;    uint8_t polarity;    uint32_t deliver_bitmask[MAX_APIC_WORDS];    for (i = 0; i < IOAPIC_NUM_PINS; i++) {        mask = 1 << i;        if (s->irr & mask) {            entry = s->ioredtbl[i];            if (!(entry & APIC_LVT_MASKED)) {                trig_mode = ((entry >> 15) & 1);                dest = entry >> 56;                dest_mode = (entry >> 11) & 1;                delivery_mode = (entry >> 8) & 7;                polarity = (entry >> 13) & 1;                if (trig_mode == APIC_TRIGGER_EDGE)                    s->irr &= ~mask;                if (delivery_mode == APIC_DM_EXTINT)                    vector = pic_read_irq(isa_pic);                else                    vector = entry & 0xff;                apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);                apic_bus_deliver(deliver_bitmask, delivery_mode,                                 vector, polarity, trig_mode);            }        }    }}void ioapic_set_irq(void *opaque, int vector, int level){    IOAPICState *s = opaque;    if (vector >= 0 && vector < IOAPIC_NUM_PINS) {        uint32_t mask = 1 << vector;        uint64_t entry = s->ioredtbl[vector];        if ((entry >> 15) & 1) {            /* level triggered */            if (level) {                s->irr |= mask;                ioapic_service(s);            } else {                s->irr &= ~mask;            }        } else {            /* edge triggered */            if (level) {                s->irr |= mask;                ioapic_service(s);            }        }    }}static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr){    IOAPICState *s = opaque;    int index;    uint32_t val = 0;    addr &= 0xff;    if (addr == 0x00) {        val = s->ioregsel;    } else if (addr == 0x10) {        switch (s->ioregsel) {            case 0x00:                val = s->id << 24;                break;            case 0x01:                val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */                break;            case 0x02:                val = 0;                break;            default:                index = (s->ioregsel - 0x10) >> 1;                if (index >= 0 && index < IOAPIC_NUM_PINS) {                    if (s->ioregsel & 1)                        val = s->ioredtbl[index] >> 32;                    else                        val = s->ioredtbl[index] & 0xffffffff;                }        }#ifdef DEBUG_IOAPIC        printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);#endif    }    return val;}static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val){    IOAPICState *s = opaque;    int index;    addr &= 0xff;    if (addr == 0x00)  {        s->ioregsel = val;        return;    } else if (addr == 0x10) {#ifdef DEBUG_IOAPIC        printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);#endif        switch (s->ioregsel) {            case 0x00:                s->id = (val >> 24) & 0xff;                return;            case 0x01:            case 0x02:                return;            default:                index = (s->ioregsel - 0x10) >> 1;                if (index >= 0 && index < IOAPIC_NUM_PINS) {                    if (s->ioregsel & 1) {                        s->ioredtbl[index] &= 0xffffffff;                        s->ioredtbl[index] |= (uint64_t)val << 32;                    } else {                        s->ioredtbl[index] &= ~0xffffffffULL;                        s->ioredtbl[index] |= val;                    }                    ioapic_service(s);                }        }    }}static void ioapic_save(QEMUFile *f, void *opaque){    IOAPICState *s = opaque;    int i;    qemu_put_8s(f, &s->id);    qemu_put_8s(f, &s->ioregsel);    for (i = 0; i < IOAPIC_NUM_PINS; i++) {        qemu_put_be64s(f, &s->ioredtbl[i]);    }}static int ioapic_load(QEMUFile *f, void *opaque, int version_id){    IOAPICState *s = opaque;    int i;    if (version_id != 1)        return -EINVAL;    qemu_get_8s(f, &s->id);    qemu_get_8s(f, &s->ioregsel);    for (i = 0; i < IOAPIC_NUM_PINS; i++) {        qemu_get_be64s(f, &s->ioredtbl[i]);    }    return 0;}static void ioapic_reset(void *opaque){    IOAPICState *s = opaque;    int i;    memset(s, 0, sizeof(*s));    for(i = 0; i < IOAPIC_NUM_PINS; i++)        s->ioredtbl[i] = 1 << 16; /* mask LVT */}static CPUReadMemoryFunc *ioapic_mem_read[3] = {    ioapic_mem_readl,    ioapic_mem_readl,    ioapic_mem_readl,};static CPUWriteMemoryFunc *ioapic_mem_write[3] = {    ioapic_mem_writel,    ioapic_mem_writel,    ioapic_mem_writel,};IOAPICState *ioapic_init(void){    IOAPICState *s;    int io_memory;    s = qemu_mallocz(sizeof(IOAPICState));    if (!s)        return NULL;    ioapic_reset(s);    s->id = last_apic_id++;    io_memory = cpu_register_io_memory(0, ioapic_mem_read,                                       ioapic_mem_write, s);    cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);    register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);    qemu_register_reset(ioapic_reset, s);    return s;}