default_config:    /* not efficient, but simple */    addr = address;    for(i = 0; i < len; i++) {        /* default read/write accesses */        switch(d->config[0x0e]) {        case 0x00:        case 0x80:            switch(addr) {            case 0x00:            case 0x01:            case 0x02:            case 0x03:            case 0x08:            case 0x09:            case 0x0a:            case 0x0b:            case 0x0e:            case 0x10 ... 0x27: /* base */            case 0x30 ... 0x33: /* rom */            case 0x3d:                can_write = 0;                break;            default:                can_write = 1;                break;            }            break;        default:        case 0x01:            switch(addr) {            case 0x00:            case 0x01:            case 0x02:            case 0x03:            case 0x08:            case 0x09:            case 0x0a:            case 0x0b:            case 0x0e:            case 0x38 ... 0x3b: /* rom */            case 0x3d:                can_write = 0;                break;            default:                can_write = 1;                break;            }            break;        }        if (can_write) {            d->config[addr] = val;        }        if (++addr > 0xff)        	break;        val >>= 8;    }    end = address + len;    if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {        /* if the command register is modified, we must modify the mappings */        pci_update_mappings(d);    }}void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len){    PCIBus *s = opaque;    PCIDevice *pci_dev;    int config_addr, bus_num;#if defined(DEBUG_PCI) && 0    printf("pci_data_write: addr=%08x val=%08x len=%d\n",           addr, val, len);#endif    bus_num = (addr >> 16) & 0xff;    while (s && s->bus_num != bus_num)        s = s->next;    if (!s)        return;    pci_dev = s->devices[(addr >> 8) & 0xff];    if (!pci_dev)        return;    config_addr = addr & 0xff;#if defined(DEBUG_PCI)    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",           pci_dev->name, config_addr, val, len);#endif    pci_dev->config_write(pci_dev, config_addr, val, len);}uint32_t pci_data_read(void *opaque, uint32_t addr, int len){    PCIBus *s = opaque;    PCIDevice *pci_dev;    int config_addr, bus_num;    uint32_t val;    bus_num = (addr >> 16) & 0xff;    while (s && s->bus_num != bus_num)        s= s->next;    if (!s)        goto fail;    pci_dev = s->devices[(addr >> 8) & 0xff];    if (!pci_dev) {    fail:        switch(len) {        case 1:            val = 0xff;            break;        case 2:            val = 0xffff;            break;        default:        case 4:            val = 0xffffffff;            break;        }        goto the_end;    }    config_addr = addr & 0xff;    val = pci_dev->config_read(pci_dev, config_addr, len);#if defined(DEBUG_PCI)    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",           pci_dev->name, config_addr, val, len);#endif the_end:#if defined(DEBUG_PCI) && 0    printf("pci_data_read: addr=%08x val=%08x len=%d\n",           addr, val, len);#endif    return val;}/***********************************************************//* generic PCI irq support *//* 0 <= irq_num <= 3. level must be 0 or 1 */static void pci_set_irq(void *opaque, int irq_num, int level){    PCIDevice *pci_dev = (PCIDevice *)opaque;    PCIBus *bus;    int change;    change = level - pci_dev->irq_state[irq_num];    if (!change)        return;    pci_dev->irq_state[irq_num] = level;    for (;;) {        bus = pci_dev->bus;        irq_num = bus->map_irq(pci_dev, irq_num);        if (bus->set_irq)            break;        pci_dev = bus->parent_dev;    }    bus->irq_count[irq_num] += change;    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);}/***********************************************************//* monitor info on PCI */typedef struct {    uint16_t class;    const char *desc;} pci_class_desc;static pci_class_desc pci_class_descriptions[] ={    { 0x0100, "SCSI controller"},    { 0x0101, "IDE controller"},    { 0x0102, "Floppy controller"},    { 0x0103, "IPI controller"},    { 0x0104, "RAID controller"},    { 0x0106, "SATA controller"},    { 0x0107, "SAS controller"},    { 0x0180, "Storage controller"},    { 0x0200, "Ethernet controller"},    { 0x0201, "Token Ring controller"},    { 0x0202, "FDDI controller"},    { 0x0203, "ATM controller"},    { 0x0280, "Network controller"},    { 0x0300, "VGA controller"},    { 0x0301, "XGA controller"},    { 0x0302, "3D controller"},    { 0x0380, "Display controller"},    { 0x0400, "Video controller"},    { 0x0401, "Audio controller"},    { 0x0402, "Phone"},    { 0x0480, "Multimedia controller"},    { 0x0500, "RAM controller"},    { 0x0501, "Flash controller"},    { 0x0580, "Memory controller"},    { 0x0600, "Host bridge"},    { 0x0601, "ISA bridge"},    { 0x0602, "EISA bridge"},    { 0x0603, "MC bridge"},    { 0x0604, "PCI bridge"},    { 0x0605, "PCMCIA bridge"},    { 0x0606, "NUBUS bridge"},    { 0x0607, "CARDBUS bridge"},    { 0x0608, "RACEWAY bridge"},    { 0x0680, "Bridge"},    { 0x0c03, "USB controller"},    { 0, NULL}};static void pci_info_device(PCIDevice *d){    int i, class;    PCIIORegion *r;    pci_class_desc *desc;    term_printf("  Bus %2d, device %3d, function %d:\n",           d->bus->bus_num, d->devfn >> 3, d->devfn & 7);    class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));    term_printf("    ");    desc = pci_class_descriptions;    while (desc->desc && class != desc->class)        desc++;    if (desc->desc) {        term_printf("%s", desc->desc);    } else {        term_printf("Class %04x", class);    }    term_printf(": PCI device %04x:%04x\n",           le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),           le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));    if (d->config[PCI_INTERRUPT_PIN] != 0) {        term_printf("      IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);    }    if (class == 0x0604) {        term_printf("      BUS %d.\n", d->config[0x19]);    }    for(i = 0;i < PCI_NUM_REGIONS; i++) {        r = &d->io_regions[i];        if (r->size != 0) {            term_printf("      BAR%d: ", i);            if (r->type & PCI_ADDRESS_SPACE_IO) {                term_printf("I/O at 0x%04x [0x%04x].\n",                       r->addr, r->addr + r->size - 1);            } else {                term_printf("32 bit memory at 0x%08x [0x%08x].\n",                       r->addr, r->addr + r->size - 1);            }        }    }    if (class == 0x0604 && d->config[0x19] != 0) {        pci_for_each_device(d->config[0x19], pci_info_device);    }}void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)){    PCIBus *bus = first_bus;    PCIDevice *d;    int devfn;    while (bus && bus->bus_num != bus_num)        bus = bus->next;    if (bus) {        for(devfn = 0; devfn < 256; devfn++) {            d = bus->devices[devfn];            if (d)                fn(d);        }    }}void pci_info(void){    pci_for_each_device(0, pci_info_device);}/* Initialize a PCI NIC.  */void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn){    if (strcmp(nd->model, "ne2k_pci") == 0) {        pci_ne2000_init(bus, nd, devfn);    } else if (strcmp(nd->model, "i82551") == 0) {        pci_i82551_init(bus, nd, devfn);    } else if (strcmp(nd->model, "i82557b") == 0) {        pci_i82557b_init(bus, nd, devfn);    } else if (strcmp(nd->model, "i82559er") == 0) {        pci_i82559er_init(bus, nd, devfn);    } else if (strcmp(nd->model, "rtl8139") == 0) {        pci_rtl8139_init(bus, nd, devfn);    } else if (strcmp(nd->model, "pcnet") == 0) {        pci_pcnet_init(bus, nd, devfn);    } else if (strcmp(nd->model, "?") == 0) {        fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"                        " ne2k_pci pcnet rtl8139\n");        exit (1);    } else {        fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);        exit (1);    }}typedef struct {    PCIDevice dev;    PCIBus *bus;} PCIBridge;static void pci_bridge_write_config(PCIDevice *d,                             uint32_t address, uint32_t val, int len){    PCIBridge *s = (PCIBridge *)d;    if (address == 0x19 || (address == 0x18 && len > 1)) {        if (address == 0x19)            s->bus->bus_num = val & 0xff;        else            s->bus->bus_num = (val >> 8) & 0xff;#if defined(DEBUG_PCI)        printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);#endif    }    pci_default_write_config(d, address, val, len);}PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,                        pci_map_irq_fn map_irq, const char *name){    PCIBridge *s;    s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),                                         devfn, NULL, pci_bridge_write_config);    s->dev.config[0x00] = id >> 16;    s->dev.config[0x01] = id >> 24;    s->dev.config[0x02] = id; // device_id    s->dev.config[0x03] = id >> 8;    s->dev.config[0x04] = 0x06; // command = bus master, pci mem    s->dev.config[0x05] = 0x00;    s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error    s->dev.config[0x07] = 0x00; // status = fast devsel    s->dev.config[0x08] = 0x00; // revision    s->dev.config[0x09] = 0x00; // programming i/f    s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge    s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge    s->dev.config[0x0D] = 0x10; // latency_timer    s->dev.config[0x0E] = 0x81; // header_type    s->dev.config[0x1E] = 0xa0; // secondary status    s->bus = pci_register_secondary_bus(&s->dev, map_irq);    return s->bus;}