}    dpy_update(s->ds, 0, 0,               s->last_scr_width, s->last_scr_height);}#define GMODE_TEXT     0#define GMODE_GRAPH    1#define GMODE_BLANK 2static void vga_update_display(void *opaque){    VGAState *s = (VGAState *)opaque;    int full_update, graphic_mode;    if (s->ds->depth == 0) {        /* nothing to do */    } else {        s->rgb_to_pixel =            rgb_to_pixel_dup_table[get_depth_index(s->ds)];        full_update = 0;        if (!(s->ar_index & 0x20)) {            graphic_mode = GMODE_BLANK;        } else {            graphic_mode = s->gr[6] & 1;        }        if (graphic_mode != s->graphic_mode) {            s->graphic_mode = graphic_mode;            full_update = 1;        }        switch(graphic_mode) {        case GMODE_TEXT:            vga_draw_text(s, full_update);            break;        case GMODE_GRAPH:            vga_draw_graphic(s, full_update);            break;        case GMODE_BLANK:        default:            vga_draw_blank(s, full_update);            break;        }    }}/* force a full display refresh */static void vga_invalidate_display(void *opaque){    VGAState *s = (VGAState *)opaque;    s->last_width = -1;    s->last_height = -1;}static void vga_reset(VGAState *s){    memset(s, 0, sizeof(VGAState));    s->graphic_mode = -1; /* force full update */}static CPUReadMemoryFunc *vga_mem_read[3] = {    vga_mem_readb,    vga_mem_readw,    vga_mem_readl,};static CPUWriteMemoryFunc *vga_mem_write[3] = {    vga_mem_writeb,    vga_mem_writew,    vga_mem_writel,};static void vga_save(QEMUFile *f, void *opaque){    VGAState *s = opaque;    int i;    if (s->pci_dev)        pci_device_save(s->pci_dev, f);    qemu_put_be32s(f, &s->latch);    qemu_put_8s(f, &s->sr_index);    qemu_put_buffer(f, s->sr, 8);    qemu_put_8s(f, &s->gr_index);    qemu_put_buffer(f, s->gr, 16);    qemu_put_8s(f, &s->ar_index);    qemu_put_buffer(f, s->ar, 21);    qemu_put_be32(f, s->ar_flip_flop);    qemu_put_8s(f, &s->cr_index);    qemu_put_buffer(f, s->cr, 256);    qemu_put_8s(f, &s->msr);    qemu_put_8s(f, &s->fcr);    qemu_put_byte(f, s->st00);    qemu_put_8s(f, &s->st01);    qemu_put_8s(f, &s->dac_state);    qemu_put_8s(f, &s->dac_sub_index);    qemu_put_8s(f, &s->dac_read_index);    qemu_put_8s(f, &s->dac_write_index);    qemu_put_buffer(f, s->dac_cache, 3);    qemu_put_buffer(f, s->palette, 768);    qemu_put_be32(f, s->bank_offset);#ifdef CONFIG_BOCHS_VBE    qemu_put_byte(f, 1);    qemu_put_be16s(f, &s->vbe_index);    for(i = 0; i < VBE_DISPI_INDEX_NB; i++)        qemu_put_be16s(f, &s->vbe_regs[i]);    qemu_put_be32s(f, &s->vbe_start_addr);    qemu_put_be32s(f, &s->vbe_line_offset);    qemu_put_be32s(f, &s->vbe_bank_mask);#else    qemu_put_byte(f, 0);#endif}static int vga_load(QEMUFile *f, void *opaque, int version_id){    VGAState *s = opaque;    int is_vbe, i, ret;    if (version_id > 2)        return -EINVAL;    if (s->pci_dev && version_id >= 2) {        ret = pci_device_load(s->pci_dev, f);        if (ret < 0)            return ret;    }    qemu_get_be32s(f, &s->latch);    qemu_get_8s(f, &s->sr_index);    qemu_get_buffer(f, s->sr, 8);    qemu_get_8s(f, &s->gr_index);    qemu_get_buffer(f, s->gr, 16);    qemu_get_8s(f, &s->ar_index);    qemu_get_buffer(f, s->ar, 21);    s->ar_flip_flop=qemu_get_be32(f);    qemu_get_8s(f, &s->cr_index);    qemu_get_buffer(f, s->cr, 256);    qemu_get_8s(f, &s->msr);    qemu_get_8s(f, &s->fcr);    qemu_get_8s(f, &s->st00);    qemu_get_8s(f, &s->st01);    qemu_get_8s(f, &s->dac_state);    qemu_get_8s(f, &s->dac_sub_index);    qemu_get_8s(f, &s->dac_read_index);    qemu_get_8s(f, &s->dac_write_index);    qemu_get_buffer(f, s->dac_cache, 3);    qemu_get_buffer(f, s->palette, 768);    s->bank_offset=qemu_get_be32(f);    is_vbe = qemu_get_byte(f);#ifdef CONFIG_BOCHS_VBE    if (!is_vbe)        return -EINVAL;    qemu_get_be16s(f, &s->vbe_index);    for(i = 0; i < VBE_DISPI_INDEX_NB; i++)        qemu_get_be16s(f, &s->vbe_regs[i]);    qemu_get_be32s(f, &s->vbe_start_addr);    qemu_get_be32s(f, &s->vbe_line_offset);    qemu_get_be32s(f, &s->vbe_bank_mask);#else    if (is_vbe)        return -EINVAL;#endif    /* force refresh */    s->graphic_mode = -1;    return 0;}typedef struct PCIVGAState {    PCIDevice dev;    VGAState vga_state;} PCIVGAState;static void vga_map(PCIDevice *pci_dev, int region_num,                    uint32_t addr, uint32_t size, int type){    PCIVGAState *d = (PCIVGAState *)pci_dev;    VGAState *s = &d->vga_state;    if (region_num == PCI_ROM_SLOT) {        cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);    } else {        cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);    }}void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,                     unsigned long vga_ram_offset, int vga_ram_size){    int i, j, v, b;    for(i = 0;i < 256; i++) {        v = 0;        for(j = 0; j < 8; j++) {            v |= ((i >> j) & 1) << (j * 4);        }        expand4[i] = v;        v = 0;        for(j = 0; j < 4; j++) {            v |= ((i >> (2 * j)) & 3) << (j * 4);        }        expand2[i] = v;    }    for(i = 0; i < 16; i++) {        v = 0;        for(j = 0; j < 4; j++) {            b = ((i >> j) & 1);            v |= b << (2 * j);            v |= b << (2 * j + 1);        }        expand4to8[i] = v;    }    vga_reset(s);    s->vram_ptr = vga_ram_base;    s->vram_offset = vga_ram_offset;    s->vram_size = vga_ram_size;    s->ds = ds;    s->get_bpp = vga_get_bpp;    s->get_offsets = vga_get_offsets;    s->get_resolution = vga_get_resolution;    s->update = vga_update_display;    s->invalidate = vga_invalidate_display;    s->screen_dump = vga_screen_dump;}/* used by both ISA and PCI */void vga_init(VGAState *s){    int vga_io_memory;    register_savevm("vga", 0, 2, vga_save, vga_load, s);    register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);    register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);    register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);    register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);    register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);    register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);    register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);    register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);    register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);    register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);    s->bank_offset = 0;#ifdef CONFIG_BOCHS_VBE    s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;    s->vbe_bank_mask = ((s->vram_size >> 16) - 1);#if defined (TARGET_I386)    register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);    register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);    register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);    register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);    /* old Bochs IO ports */    register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);    register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);    register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);    register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);#else    register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);    register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);    register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);    register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);#endif#endif /* CONFIG_BOCHS_VBE */    vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);    cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,                                 vga_io_memory);}/* Memory mapped interface */static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr){    VGAState *s = opaque;    return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xff;}static void vga_mm_writeb (void *opaque,                           target_phys_addr_t addr, uint32_t value){    VGAState *s = opaque;    vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xff);}static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr){    VGAState *s = opaque;    return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift) & 0xffff;}static void vga_mm_writew (void *opaque,                           target_phys_addr_t addr, uint32_t value){    VGAState *s = opaque;    vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value & 0xffff);}static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr){    VGAState *s = opaque;    return vga_ioport_read(s, (addr - s->base_ctrl) >> s->it_shift);}static void vga_mm_writel (void *opaque,                           target_phys_addr_t addr, uint32_t value){    VGAState *s = opaque;    vga_ioport_write(s, (addr - s->base_ctrl) >> s->it_shift, value);}static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {    &vga_mm_readb,    &vga_mm_readw,    &vga_mm_readl,};static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {    &vga_mm_writeb,    &vga_mm_writew,    &vga_mm_writel,};static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,                        target_phys_addr_t ctrl_base, int it_shift){    int s_ioport_ctrl, vga_io_memory;    s->base_ctrl = ctrl_base;    s->it_shift = it_shift;    s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);    vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);    register_savevm("vga", 0, 2, vga_save, vga_load, s);    cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);    s->bank_offset = 0;    cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);}int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,                 unsigned long vga_ram_offset, int vga_ram_size){    VGAState *s;    s = qemu_mallocz(sizeof(VGAState));    if (!s)        return -1;    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);    vga_init(s);    graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);#ifdef CONFIG_BOCHS_VBE    /* XXX: use optimized standard vga accesses */    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,                                 vga_ram_size, vga_ram_offset);#endif    return 0;}int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,                    unsigned long vga_ram_offset, int vga_ram_size,                    target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,                    int it_shift){    VGAState *s;    s = qemu_mallocz(sizeof(VGAState));    if (!s)        return -1;    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);    vga_mm_init(s, vram_base, ctrl_base, it_shift);    graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);#ifdef CONFIG_BOCHS_VBE    /* XXX: use optimized standard vga accesses */    cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,                                 vga_ram_size, vga_ram_offset);#endif    return 0;}int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,                 unsigned long vga_ram_offset, int vga_ram_size,                 unsigned long vga_bios_offset, int vga_bios_size){    PCIVGAState *d;    VGAState *s;    uint8_t *pci_conf;    d = (PCIVGAState *)pci_register_device(bus, "VGA",                                           sizeof(PCIVGAState),                                           -1, NULL, NULL);    if (!d)        return -1;    s = &d->vga_state;    vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);    vga_init(s);    graphic_console_init(s->ds, s->update, s->invalidate, s->screen_dump, s);    s->pci_dev = &d->dev;    pci_conf = d->dev.config;    pci_conf[0x00] = 0x34; // dummy VGA (same as Bochs ID)    pci_conf[0x01] = 0x12;    pci_conf[0x02] = 0x11;    pci_conf[0x03] = 0x11;    pci_conf[0x0a] = 0x00; // VGA controller    pci_conf[0x0b] = 0x03;    pci_conf[0x0e] = 0x00; // header_type    /* XXX: vga_ram_size must be a power of two */    pci_register_io_region(&d->dev, 0, vga_ram_size,                           PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);    if (vga_bios_size != 0) {        unsigned int bios_total_size;        s->bios_offset = vga_bios_offset;        s->bios_size = vga_bios_size;        /* must be a power of two */        bios_total_size = 1;        while (bios_total_size < vga_bios_size)            bios_total_size <<= 1;        pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,                               PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);    }    return 0;}/********************************************************//* vga screen dump */static int vga_save_w, vga_save_h;static void vga_save_dpy_update(DisplayState *s,                                int x, int y, int w, int h){}static void vga_save_dpy_resize(DisplayState *s, int w, int h){    s->linesize = w * 4;    s->data = qemu_malloc(h * s->linesize);    vga_save_w = w;    vga_save_h = h;}static void vga_save_dpy_refresh(DisplayState *s){}int ppm_save(const char *filename, uint8_t *data,             int w, int h, int linesize){    FILE *f;    uint8_t *d, *d1;    unsigned int v;    int y, x;    f = fopen(filename, "wb");    if (!f)        return -1;    fprintf(f, "P6\n%d %d\n%d\n",            w, h, 255);    d1 = data;    for(y = 0; y < h; y++) {        d = d1;        for(x = 0; x < w; x++) {            v = *(uint32_t *)d;            fputc((v >> 16) & 0xff, f);            fputc((v >> 8) & 0xff, f);            fputc((v) & 0xff, f);            d += 4;        }        d1 += linesize;    }    fclose(f);    return 0;}/* save the vga display in a PPM image even if no display is   available */static void vga_screen_dump(void *opaque, const char *filename){    VGAState *s = (VGAState *)opaque;    DisplayState *saved_ds, ds1, *ds = &ds1;    /* XXX: this is a little hackish */    vga_invalidate_display(s);    saved_ds = s->ds;    memset(ds, 0, sizeof(DisplayState));    ds->dpy_update = vga_save_dpy_update;    ds->dpy_resize = vga_save_dpy_resize;    ds->dpy_refresh = vga_save_dpy_refresh;    ds->depth = 32;    s->ds = ds;    s->graphic_mode = -1;    vga_update_display(s);    if (ds->data) {        ppm_save(filename, ds->data, vga_save_w, vga_save_h,                 s->ds->linesize);        qemu_free(ds->data);    }    s->ds = saved_ds;}