tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);#if defined(PPC_DEBUG_TB)    if (loglevel != 0) {        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);    }#endif    return tb >> 32;}uint32_t cpu_ppc_load_tbu (CPUState *env){    return _cpu_ppc_load_tbu(env);}static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,                                            int64_t *tb_offsetp,                                            uint64_t value){    *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",                __func__, value, *tb_offsetp);    }#endif}void cpu_ppc_store_tbl (CPUState *env, uint32_t value){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);    tb &= 0xFFFFFFFF00000000ULL;    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),                     &tb_env->tb_offset, tb | (uint64_t)value);}static always_inline void _cpu_ppc_store_tbu (CPUState *env, uint32_t value){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);    tb &= 0x00000000FFFFFFFFULL;    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),                     &tb_env->tb_offset, ((uint64_t)value << 32) | tb);}void cpu_ppc_store_tbu (CPUState *env, uint32_t value){    _cpu_ppc_store_tbu(env, value);}uint32_t cpu_ppc_load_atbl (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);#if defined(PPC_DEBUG_TB)    if (loglevel != 0) {        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);    }#endif    return tb & 0xFFFFFFFF;}uint32_t cpu_ppc_load_atbu (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);#if defined(PPC_DEBUG_TB)    if (loglevel != 0) {        fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);    }#endif    return tb >> 32;}void cpu_ppc_store_atbl (CPUState *env, uint32_t value){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);    tb &= 0xFFFFFFFF00000000ULL;    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),                     &tb_env->atb_offset, tb | (uint64_t)value);}void cpu_ppc_store_atbu (CPUState *env, uint32_t value){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb;    tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);    tb &= 0x00000000FFFFFFFFULL;    cpu_ppc_store_tb(tb_env, qemu_get_clock(vm_clock),                     &tb_env->atb_offset, ((uint64_t)value << 32) | tb);}static void cpu_ppc_tb_stop (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb, atb, vmclk;    /* If the time base is already frozen, do nothing */    if (tb_env->tb_freq != 0) {        vmclk = qemu_get_clock(vm_clock);        /* Get the time base */        tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset);        /* Get the alternate time base */        atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset);        /* Store the time base value (ie compute the current offset) */        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);        /* Store the alternate time base value (compute the current offset) */        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);        /* Set the time base frequency to zero */        tb_env->tb_freq = 0;        /* Now, the time bases are frozen to tb_offset / atb_offset value */    }}static void cpu_ppc_tb_start (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    uint64_t tb, atb, vmclk;    /* If the time base is not frozen, do nothing */    if (tb_env->tb_freq == 0) {        vmclk = qemu_get_clock(vm_clock);        /* Get the time base from tb_offset */        tb = tb_env->tb_offset;        /* Get the alternate time base from atb_offset */        atb = tb_env->atb_offset;        /* Restore the tb frequency from the decrementer frequency */        tb_env->tb_freq = tb_env->decr_freq;        /* Store the time base value */        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb);        /* Store the alternate time base value */        cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb);    }}static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,                                                  uint64_t *next){    ppc_tb_t *tb_env = env->tb_env;    uint32_t decr;    int64_t diff;    diff = tb_env->decr_next - qemu_get_clock(vm_clock);    if (diff >= 0)        decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec);    else        decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);#if defined(PPC_DEBUG_TB)    if (loglevel != 0) {        fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);    }#endif    return decr;}uint32_t cpu_ppc_load_decr (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    return _cpu_ppc_load_decr(env, &tb_env->decr_next);}uint32_t cpu_ppc_load_hdecr (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    return _cpu_ppc_load_decr(env, &tb_env->hdecr_next);}uint64_t cpu_ppc_load_purr (CPUState *env){    ppc_tb_t *tb_env = env->tb_env;    uint64_t diff;    diff = qemu_get_clock(vm_clock) - tb_env->purr_start;    return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, ticks_per_sec);}/* When decrementer expires, * all we need to do is generate or queue a CPU exception */static always_inline void cpu_ppc_decr_excp (CPUState *env){    /* Raise it */#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "raise decrementer exception\n");    }#endif    ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);}static always_inline void cpu_ppc_hdecr_excp (CPUState *env){    /* Raise it */#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "raise decrementer exception\n");    }#endif    ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);}static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,                                  struct QEMUTimer *timer,                                  void (*raise_excp)(CPUState *),                                  uint32_t decr, uint32_t value,                                  int is_excp){    ppc_tb_t *tb_env = env->tb_env;    uint64_t now, next;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,                decr, value);    }#endif    now = qemu_get_clock(vm_clock);    next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq);    if (is_excp)        next += *nextp - now;    if (next == now)        next++;    *nextp = next;    /* Adjust timer */    qemu_mod_timer(timer, next);    /* If we set a negative value and the decrementer was positive,     * raise an exception.     */    if ((value & 0x80000000) && !(decr & 0x80000000))        (*raise_excp)(env);}static always_inline void _cpu_ppc_store_decr (CPUState *env, uint32_t decr,                                               uint32_t value, int is_excp){    ppc_tb_t *tb_env = env->tb_env;    __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer,                         &cpu_ppc_decr_excp, decr, value, is_excp);}void cpu_ppc_store_decr (CPUState *env, uint32_t value){    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);}static void cpu_ppc_decr_cb (void *opaque){    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);}static always_inline void _cpu_ppc_store_hdecr (CPUState *env, uint32_t hdecr,                                                uint32_t value, int is_excp){    ppc_tb_t *tb_env = env->tb_env;    if (tb_env->hdecr_timer != NULL) {        __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer,                             &cpu_ppc_hdecr_excp, hdecr, value, is_excp);    }}void cpu_ppc_store_hdecr (CPUState *env, uint32_t value){    _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);}static void cpu_ppc_hdecr_cb (void *opaque){    _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);}void cpu_ppc_store_purr (CPUState *env, uint64_t value){    ppc_tb_t *tb_env = env->tb_env;    tb_env->purr_load = value;    tb_env->purr_start = qemu_get_clock(vm_clock);}static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq){    CPUState *env = opaque;    ppc_tb_t *tb_env = env->tb_env;    tb_env->tb_freq = freq;    tb_env->decr_freq = freq;    /* There is a bug in Linux 2.4 kernels:     * if a decrementer exception is pending when it enables msr_ee at startup,     * it's not ready to handle it...     */    _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);    _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0);    cpu_ppc_store_purr(env, 0x0000000000000000ULL);}/* Set up (once) timebase frequency (in Hz) */clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq){    ppc_tb_t *tb_env;    tb_env = qemu_mallocz(sizeof(ppc_tb_t));    if (tb_env == NULL)        return NULL;    env->tb_env = tb_env;    /* Create new timer */    tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_ppc_decr_cb, env);    if (0) {        /* XXX: find a suitable condition to enable the hypervisor decrementer         */        tb_env->hdecr_timer = qemu_new_timer(vm_clock, &cpu_ppc_hdecr_cb, env);    } else {        tb_env->hdecr_timer = NULL;    }    cpu_ppc_set_tb_clk(env, freq);    return &cpu_ppc_set_tb_clk;}/* Specific helpers for POWER & PowerPC 601 RTC */clk_setup_cb cpu_ppc601_rtc_init (CPUState *env){    return cpu_ppc_tb_init(env, 7812500);}void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value){    _cpu_ppc_store_tbu(env, value);}uint32_t cpu_ppc601_load_rtcu (CPUState *env){    return _cpu_ppc_load_tbu(env);}void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value){    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);}uint32_t cpu_ppc601_load_rtcl (CPUState *env){    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;}/*****************************************************************************//* Embedded PowerPC timers *//* PIT, FIT & WDT */typedef struct ppcemb_timer_t ppcemb_timer_t;struct ppcemb_timer_t {    uint64_t pit_reload;  /* PIT auto-reload value        */    uint64_t fit_next;    /* Tick for next FIT interrupt  */    struct QEMUTimer *fit_timer;    uint64_t wdt_next;    /* Tick for next WDT interrupt  */    struct QEMUTimer *wdt_timer;};/* Fixed interval timer */static void cpu_4xx_fit_cb (void *opaque){    CPUState *env;    ppc_tb_t *tb_env;    ppcemb_timer_t *ppcemb_timer;    uint64_t now, next;    env = opaque;    tb_env = env->tb_env;    ppcemb_timer = tb_env->opaque;    now = qemu_get_clock(vm_clock);    switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) {    case 0:        next = 1 << 9;        break;    case 1:        next = 1 << 13;        break;    case 2:        next = 1 << 17;        break;    case 3:        next = 1 << 21;        break;    default:        /* Cannot occur, but makes gcc happy */        return;    }    next = now + muldiv64(next, ticks_per_sec, tb_env->tb_freq);    if (next == now)        next++;    qemu_mod_timer(ppcemb_timer->fit_timer, next);    env->spr[SPR_40x_TSR] |= 1 << 26;    if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)        ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,                (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);    }#endif}/* Programmable interval timer */static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp){    ppcemb_timer_t *ppcemb_timer;    uint64_t now, next;    ppcemb_timer = tb_env->opaque;    if (ppcemb_timer->pit_reload <= 1 ||        !((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||        (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {        /* Stop PIT */#ifdef PPC_DEBUG_TB        if (loglevel != 0) {            fprintf(logfile, "%s: stop PIT\n", __func__);        }#endif        qemu_del_timer(tb_env->decr_timer);    } else {#ifdef PPC_DEBUG_TB        if (loglevel != 0) {            fprintf(logfile, "%s: start PIT %016" PRIx64 "\n",                    __func__, ppcemb_timer->pit_reload);        }#endif        now = qemu_get_clock(vm_clock);        next = now + muldiv64(ppcemb_timer->pit_reload,                              ticks_per_sec, tb_env->decr_freq);        if (is_excp)            next += tb_env->decr_next - now;        if (next == now)            next++;        qemu_mod_timer(tb_env->decr_timer, next);        tb_env->decr_next = next;    }}static void cpu_4xx_pit_cb (void *opaque){    CPUState *env;    ppc_tb_t *tb_env;    ppcemb_timer_t *ppcemb_timer;    env = opaque;    tb_env = env->tb_env;    ppcemb_timer = tb_env->opaque;    env->spr[SPR_40x_TSR] |= 1 << 27;    if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)