ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);    start_stop_pit(env, tb_env, 1);#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "                "%016" PRIx64 "\n", __func__,                (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),                (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],                ppcemb_timer->pit_reload);    }#endif}/* Watchdog timer */static void cpu_4xx_wdt_cb (void *opaque){    CPUState *env;    ppc_tb_t *tb_env;    ppcemb_timer_t *ppcemb_timer;    uint64_t now, next;    env = opaque;    tb_env = env->tb_env;    ppcemb_timer = tb_env->opaque;    now = qemu_get_clock(vm_clock);    switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) {    case 0:        next = 1 << 17;        break;    case 1:        next = 1 << 21;        break;    case 2:        next = 1 << 25;        break;    case 3:        next = 1 << 29;        break;    default:        /* Cannot occur, but makes gcc happy */        return;    }    next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);    if (next == now)        next++;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,                env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);    }#endif    switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {    case 0x0:    case 0x1:        qemu_mod_timer(ppcemb_timer->wdt_timer, next);        ppcemb_timer->wdt_next = next;        env->spr[SPR_40x_TSR] |= 1 << 31;        break;    case 0x2:        qemu_mod_timer(ppcemb_timer->wdt_timer, next);        ppcemb_timer->wdt_next = next;        env->spr[SPR_40x_TSR] |= 1 << 30;        if ((env->spr[SPR_40x_TCR] >> 27) & 0x1)            ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);        break;    case 0x3:        env->spr[SPR_40x_TSR] &= ~0x30000000;        env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;        switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) {        case 0x0:            /* No reset */            break;        case 0x1: /* Core reset */            ppc40x_core_reset(env);            break;        case 0x2: /* Chip reset */            ppc40x_chip_reset(env);            break;        case 0x3: /* System reset */            ppc40x_system_reset(env);            break;        }    }}void store_40x_pit (CPUState *env, target_ulong val){    ppc_tb_t *tb_env;    ppcemb_timer_t *ppcemb_timer;    tb_env = env->tb_env;    ppcemb_timer = tb_env->opaque;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s val" ADDRX "\n", __func__, val);    }#endif    ppcemb_timer->pit_reload = val;    start_stop_pit(env, tb_env, 0);}target_ulong load_40x_pit (CPUState *env){    return cpu_ppc_load_decr(env);}void store_booke_tsr (CPUState *env, target_ulong val){#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);    }#endif    env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);    if (val & 0x80000000)        ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);}void store_booke_tcr (CPUState *env, target_ulong val){    ppc_tb_t *tb_env;    tb_env = env->tb_env;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);    }#endif    env->spr[SPR_40x_TCR] = val & 0xFFC00000;    start_stop_pit(env, tb_env, 1);    cpu_4xx_wdt_cb(env);}static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq){    CPUState *env = opaque;    ppc_tb_t *tb_env = env->tb_env;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__,                freq);    }#endif    tb_env->tb_freq = freq;    tb_env->decr_freq = freq;    /* XXX: we should also update all timers */}clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq){    ppc_tb_t *tb_env;    ppcemb_timer_t *ppcemb_timer;    tb_env = qemu_mallocz(sizeof(ppc_tb_t));    if (tb_env == NULL) {        return NULL;    }    env->tb_env = tb_env;    ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));    tb_env->tb_freq = freq;    tb_env->decr_freq = freq;    tb_env->opaque = ppcemb_timer;#ifdef PPC_DEBUG_TB    if (loglevel != 0) {        fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);    }#endif    if (ppcemb_timer != NULL) {        /* We use decr timer for PIT */        tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);        ppcemb_timer->fit_timer =            qemu_new_timer(vm_clock, &cpu_4xx_fit_cb, env);        ppcemb_timer->wdt_timer =            qemu_new_timer(vm_clock, &cpu_4xx_wdt_cb, env);    }    return &ppc_emb_set_tb_clk;}/*****************************************************************************//* Embedded PowerPC Device Control Registers */typedef struct ppc_dcrn_t ppc_dcrn_t;struct ppc_dcrn_t {    dcr_read_cb dcr_read;    dcr_write_cb dcr_write;    void *opaque;};/* XXX: on 460, DCR addresses are 32 bits wide, *      using DCRIPR to get the 22 upper bits of the DCR address */#define DCRN_NB 1024struct ppc_dcr_t {    ppc_dcrn_t dcrn[DCRN_NB];    int (*read_error)(int dcrn);    int (*write_error)(int dcrn);};int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp){    ppc_dcrn_t *dcr;    if (dcrn < 0 || dcrn >= DCRN_NB)        goto error;    dcr = &dcr_env->dcrn[dcrn];    if (dcr->dcr_read == NULL)        goto error;    *valp = (*dcr->dcr_read)(dcr->opaque, dcrn);    return 0; error:    if (dcr_env->read_error != NULL)        return (*dcr_env->read_error)(dcrn);    return -1;}int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val){    ppc_dcrn_t *dcr;    if (dcrn < 0 || dcrn >= DCRN_NB)        goto error;    dcr = &dcr_env->dcrn[dcrn];    if (dcr->dcr_write == NULL)        goto error;    (*dcr->dcr_write)(dcr->opaque, dcrn, val);    return 0; error:    if (dcr_env->write_error != NULL)        return (*dcr_env->write_error)(dcrn);    return -1;}int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,                      dcr_read_cb dcr_read, dcr_write_cb dcr_write){    ppc_dcr_t *dcr_env;    ppc_dcrn_t *dcr;    dcr_env = env->dcr_env;    if (dcr_env == NULL)        return -1;    if (dcrn < 0 || dcrn >= DCRN_NB)        return -1;    dcr = &dcr_env->dcrn[dcrn];    if (dcr->opaque != NULL ||        dcr->dcr_read != NULL ||        dcr->dcr_write != NULL)        return -1;    dcr->opaque = opaque;    dcr->dcr_read = dcr_read;    dcr->dcr_write = dcr_write;    return 0;}int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),                  int (*write_error)(int dcrn)){    ppc_dcr_t *dcr_env;    dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));    if (dcr_env == NULL)        return -1;    dcr_env->read_error = read_error;    dcr_env->write_error = write_error;    env->dcr_env = dcr_env;    return 0;}#if 0/*****************************************************************************//* Handle system reset (for now, just stop emulation) */void cpu_ppc_reset (CPUState *env){    printf("Reset asked... Stop emulation\n");    abort();}#endif/*****************************************************************************//* Debug port */void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val){    addr &= 0xF;    switch (addr) {    case 0:        printf("%c", val);        break;    case 1:        printf("\n");        fflush(stdout);        break;    case 2:        printf("Set loglevel to %04" PRIx32 "\n", val);        cpu_set_log(val | 0x100);        break;    }}/*****************************************************************************//* NVRAM helpers */static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr){    return (*nvram->read_fn)(nvram->opaque, addr);;}static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val){    (*nvram->write_fn)(nvram->opaque, addr, val);}void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value){    nvram_write(nvram, addr, value);}uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr){    return nvram_read(nvram, addr);}void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value){    nvram_write(nvram, addr, value >> 8);    nvram_write(nvram, addr + 1, value & 0xFF);}uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr){    uint16_t tmp;    tmp = nvram_read(nvram, addr) << 8;    tmp |= nvram_read(nvram, addr + 1);    return tmp;}void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value){    nvram_write(nvram, addr, value >> 24);    nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);    nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);    nvram_write(nvram, addr + 3, value & 0xFF);}uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr){    uint32_t tmp;    tmp = nvram_read(nvram, addr) << 24;    tmp |= nvram_read(nvram, addr + 1) << 16;    tmp |= nvram_read(nvram, addr + 2) << 8;    tmp |= nvram_read(nvram, addr + 3);    return tmp;}void NVRAM_set_string (nvram_t *nvram, uint32_t addr,                       const unsigned char *str, uint32_t max){    int i;    for (i = 0; i < max && str[i] != '\0'; i++) {        nvram_write(nvram, addr + i, str[i]);    }    nvram_write(nvram, addr + i, str[i]);    nvram_write(nvram, addr + max - 1, '\0');}int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max){    int i;    memset(dst, 0, max);    for (i = 0; i < max; i++) {        dst[i] = NVRAM_get_byte(nvram, addr + i);        if (dst[i] == '\0')            break;    }    return i;}static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value){    uint16_t tmp;    uint16_t pd, pd1, pd2;    tmp = prev >> 8;    pd = prev ^ value;    pd1 = pd & 0x000F;    pd2 = ((pd >> 4) & 0x000F) ^ pd1;    tmp ^= (pd1 << 3) | (pd1 << 8);    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);    return tmp;}uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count){    uint32_t i;    uint16_t crc = 0xFFFF;    int odd;    odd = count & 1;    count &= ~1;    for (i = 0; i != count; i++) {        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));    }    if (odd) {        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);    }    return crc;}#define CMDLINE_ADDR 0x017ff000int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,                          const unsigned char *arch,                          uint32_t RAM_size, int boot_device,                          uint32_t kernel_image, uint32_t kernel_size,                          const char *cmdline,                          uint32_t initrd_image, uint32_t initrd_size,                          uint32_t NVRAM_image,                          int width, int height, int depth){    uint16_t crc;    /* Set parameters for Open Hack'Ware BIOS */    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */    NVRAM_set_word(nvram,   0x14, NVRAM_size);    NVRAM_set_string(nvram, 0x20, arch, 16);    NVRAM_set_lword(nvram,  0x30, RAM_size);    NVRAM_set_byte(nvram,   0x34, boot_device);    NVRAM_set_lword(nvram,  0x38, kernel_image);    NVRAM_set_lword(nvram,  0x3C, kernel_size);    if (cmdline) {        /* XXX: put the cmdline in NVRAM too ? */        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));    } else {        NVRAM_set_lword(nvram,  0x40, 0);        NVRAM_set_lword(nvram,  0x44, 0);    }    NVRAM_set_lword(nvram,  0x48, initrd_image);    NVRAM_set_lword(nvram,  0x4C, initrd_size);    NVRAM_set_lword(nvram,  0x50, NVRAM_image);    NVRAM_set_word(nvram,   0x54, width);    NVRAM_set_word(nvram,   0x56, height);    NVRAM_set_word(nvram,   0x58, depth);    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);    NVRAM_set_word(nvram,   0xFC, crc);    return 0;}