/* *  PowerPC emulation cpu definitions for qemu. * *  Copyright (c) 2003-2007 Jocelyn Mayer * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */#if !defined (__CPU_PPC_H__)#define __CPU_PPC_H__#include "config.h"#include <inttypes.h>//#define PPC_EMULATE_32BITS_HYPV#if defined (TARGET_PPC64)/* PowerPC 64 definitions */typedef uint64_t ppc_gpr_t;#define TARGET_LONG_BITS 64#define TARGET_PAGE_BITS 12#else /* defined (TARGET_PPC64) *//* PowerPC 32 definitions */#if (HOST_LONG_BITS >= 64)/* When using 64 bits temporary registers, * we can use 64 bits GPR with no extra cost * It's even an optimization as this will prevent * the compiler to do unuseful masking in the micro-ops. */typedef uint64_t ppc_gpr_t;#else /* (HOST_LONG_BITS >= 64) */typedef uint32_t ppc_gpr_t;#endif /* (HOST_LONG_BITS >= 64) */#define TARGET_LONG_BITS 32#if defined(TARGET_PPCEMB)/* Specific definitions for PowerPC embedded *//* BookE have 36 bits physical address space */#define TARGET_PHYS_ADDR_BITS 64#if defined(CONFIG_USER_ONLY)/* It looks like a lot of Linux programs assume page size * is 4kB long. This is evil, but we have to deal with it... */#define TARGET_PAGE_BITS 12#else /* defined(CONFIG_USER_ONLY) *//* Pages can be 1 kB small */#define TARGET_PAGE_BITS 10#endif /* defined(CONFIG_USER_ONLY) */#else /* defined(TARGET_PPCEMB) *//* "standard" PowerPC 32 definitions */#define TARGET_PAGE_BITS 12#endif /* defined(TARGET_PPCEMB) */#endif /* defined (TARGET_PPC64) */#include "cpu-defs.h"#define REGX "%016" PRIx64#define ADDRX TARGET_FMT_lx#define PADDRX TARGET_FMT_plx#include <setjmp.h>#include "softfloat.h"#define TARGET_HAS_ICE 1#if defined (TARGET_PPC64)#define ELF_MACHINE     EM_PPC64#else#define ELF_MACHINE     EM_PPC#endif/*****************************************************************************//* MMU model                                                                 */typedef enum powerpc_mmu_t powerpc_mmu_t;enum powerpc_mmu_t {    POWERPC_MMU_UNKNOWN    = 0x00000000,    /* Standard 32 bits PowerPC MMU                            */    POWERPC_MMU_32B        = 0x00000001,    /* PowerPC 6xx MMU with software TLB                       */    POWERPC_MMU_SOFT_6xx   = 0x00000002,    /* PowerPC 74xx MMU with software TLB                      */    POWERPC_MMU_SOFT_74xx  = 0x00000003,    /* PowerPC 4xx MMU with software TLB                       */    POWERPC_MMU_SOFT_4xx   = 0x00000004,    /* PowerPC 4xx MMU with software TLB and zones protections */    POWERPC_MMU_SOFT_4xx_Z = 0x00000005,    /* PowerPC MMU in real mode only                           */    POWERPC_MMU_REAL       = 0x00000006,    /* Freescale MPC8xx MMU model                              */    POWERPC_MMU_MPC8xx     = 0x00000007,    /* BookE MMU model                                         */    POWERPC_MMU_BOOKE      = 0x00000008,    /* BookE FSL MMU model                                     */    POWERPC_MMU_BOOKE_FSL  = 0x00000009,    /* PowerPC 601 MMU model (specific BATs format)            */    POWERPC_MMU_601        = 0x0000000A,#if defined(TARGET_PPC64)#define POWERPC_MMU_64       0x00010000    /* 64 bits PowerPC MMU                                     */    POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,    /* 620 variant (no segment exceptions)                     */    POWERPC_MMU_620        = POWERPC_MMU_64 | 0x00000002,#endif /* defined(TARGET_PPC64) */};/*****************************************************************************//* Exception model                                                           */typedef enum powerpc_excp_t powerpc_excp_t;enum powerpc_excp_t {    POWERPC_EXCP_UNKNOWN   = 0,    /* Standard PowerPC exception model */    POWERPC_EXCP_STD,    /* PowerPC 40x exception model      */    POWERPC_EXCP_40x,    /* PowerPC 601 exception model      */    POWERPC_EXCP_601,    /* PowerPC 602 exception model      */    POWERPC_EXCP_602,    /* PowerPC 603 exception model      */    POWERPC_EXCP_603,    /* PowerPC 603e exception model     */    POWERPC_EXCP_603E,    /* PowerPC G2 exception model       */    POWERPC_EXCP_G2,    /* PowerPC 604 exception model      */    POWERPC_EXCP_604,    /* PowerPC 7x0 exception model      */    POWERPC_EXCP_7x0,    /* PowerPC 7x5 exception model      */    POWERPC_EXCP_7x5,    /* PowerPC 74xx exception model     */    POWERPC_EXCP_74xx,    /* BookE exception model            */    POWERPC_EXCP_BOOKE,#if defined(TARGET_PPC64)    /* PowerPC 970 exception model      */    POWERPC_EXCP_970,#endif /* defined(TARGET_PPC64) */};/*****************************************************************************//* Exception vectors definitions                                             */enum {    POWERPC_EXCP_NONE    = -1,    /* The 64 first entries are used by the PowerPC embedded specification   */    POWERPC_EXCP_CRITICAL = 0,  /* Critical input                            */    POWERPC_EXCP_MCHECK   = 1,  /* Machine check exception                   */    POWERPC_EXCP_DSI      = 2,  /* Data storage exception                    */    POWERPC_EXCP_ISI      = 3,  /* Instruction storage exception             */    POWERPC_EXCP_EXTERNAL = 4,  /* External input                            */    POWERPC_EXCP_ALIGN    = 5,  /* Alignment exception                       */    POWERPC_EXCP_PROGRAM  = 6,  /* Program exception                         */    POWERPC_EXCP_FPU      = 7,  /* Floating-point unavailable exception      */    POWERPC_EXCP_SYSCALL  = 8,  /* System call exception                     */    POWERPC_EXCP_APU      = 9,  /* Auxiliary processor unavailable           */    POWERPC_EXCP_DECR     = 10, /* Decrementer exception                     */    POWERPC_EXCP_FIT      = 11, /* Fixed-interval timer interrupt            */    POWERPC_EXCP_WDT      = 12, /* Watchdog timer interrupt                  */    POWERPC_EXCP_DTLB     = 13, /* Data TLB miss                             */    POWERPC_EXCP_ITLB     = 14, /* Instruction TLB miss                      */    POWERPC_EXCP_DEBUG    = 15, /* Debug interrupt                           */    /* Vectors 16 to 31 are reserved                                         */    POWERPC_EXCP_SPEU     = 32, /* SPE/embedded floating-point unavailable   */    POWERPC_EXCP_EFPDI    = 33, /* Embedded floating-point data interrupt    */    POWERPC_EXCP_EFPRI    = 34, /* Embedded floating-point round interrupt   */    POWERPC_EXCP_EPERFM   = 35, /* Embedded performance monitor interrupt    */    POWERPC_EXCP_DOORI    = 36, /* Embedded doorbell interrupt               */    POWERPC_EXCP_DOORCI   = 37, /* Embedded doorbell critical interrupt      */    /* Vectors 38 to 63 are reserved                                         */    /* Exceptions defined in the PowerPC server specification                */    POWERPC_EXCP_RESET    = 64, /* System reset exception                    */    POWERPC_EXCP_DSEG     = 65, /* Data segment exception                    */    POWERPC_EXCP_ISEG     = 66, /* Instruction segment exception             */    POWERPC_EXCP_HDECR    = 67, /* Hypervisor decrementer exception          */    POWERPC_EXCP_TRACE    = 68, /* Trace exception                           */    POWERPC_EXCP_HDSI     = 69, /* Hypervisor data storage exception         */    POWERPC_EXCP_HISI     = 70, /* Hypervisor instruction storage exception  */    POWERPC_EXCP_HDSEG    = 71, /* Hypervisor data segment exception         */    POWERPC_EXCP_HISEG    = 72, /* Hypervisor instruction segment exception  */    POWERPC_EXCP_VPU      = 73, /* Vector unavailable exception              */    /* 40x specific exceptions                                               */    POWERPC_EXCP_PIT      = 74, /* Programmable interval timer interrupt     */    /* 601 specific exceptions                                               */    POWERPC_EXCP_IO       = 75, /* IO error exception                        */    POWERPC_EXCP_RUNM     = 76, /* Run mode exception                        */    /* 602 specific exceptions                                               */    POWERPC_EXCP_EMUL     = 77, /* Emulation trap exception                  */    /* 602/603 specific exceptions                                           */    POWERPC_EXCP_IFTLB    = 78, /* Instruction fetch TLB miss                */    POWERPC_EXCP_DLTLB    = 79, /* Data load TLB miss                        */    POWERPC_EXCP_DSTLB    = 80, /* Data store TLB miss                       */    /* Exceptions available on most PowerPC                                  */    POWERPC_EXCP_FPA      = 81, /* Floating-point assist exception           */    POWERPC_EXCP_DABR     = 82, /* Data address breakpoint                   */    POWERPC_EXCP_IABR     = 83, /* Instruction address breakpoint            */    POWERPC_EXCP_SMI      = 84, /* System management interrupt               */    POWERPC_EXCP_PERFM    = 85, /* Embedded performance monitor interrupt    */    /* 7xx/74xx specific exceptions                                          */    POWERPC_EXCP_THERM    = 86, /* Thermal interrupt                         */    /* 74xx specific exceptions                                              */    POWERPC_EXCP_VPUA     = 87, /* Vector assist exception                   */    /* 970FX specific exceptions                                             */    POWERPC_EXCP_SOFTP    = 88, /* Soft patch exception                      */    POWERPC_EXCP_MAINT    = 89, /* Maintenance exception                     */    /* Freescale embeded cores specific exceptions                           */    POWERPC_EXCP_MEXTBR   = 90, /* Maskable external breakpoint              */    POWERPC_EXCP_NMEXTBR  = 91, /* Non maskable external breakpoint          */    POWERPC_EXCP_ITLBE    = 92, /* Instruction TLB error                     */    POWERPC_EXCP_DTLBE    = 93, /* Data TLB error                            */    /* EOL                                                                   */    POWERPC_EXCP_NB       = 96,    /* Qemu exceptions: used internally during code translation              */    POWERPC_EXCP_STOP         = 0x200, /* stop translation                   */    POWERPC_EXCP_BRANCH       = 0x201, /* branch instruction                 */    /* Qemu exceptions: special cases we want to stop translation            */    POWERPC_EXCP_SYNC         = 0x202, /* context synchronizing instruction  */    POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only      */};/* Exceptions error codes                                                    */enum {    /* Exception subtypes for POWERPC_EXCP_ALIGN                             */    POWERPC_EXCP_ALIGN_FP      = 0x01,  /* FP alignment exception            */    POWERPC_EXCP_ALIGN_LST     = 0x02,  /* Unaligned mult/extern load/store  */    POWERPC_EXCP_ALIGN_LE      = 0x03,  /* Multiple little-endian access     */    POWERPC_EXCP_ALIGN_PROT    = 0x04,  /* Access cross protection boundary  */    POWERPC_EXCP_ALIGN_BAT     = 0x05,  /* Access cross a BAT/seg boundary   */    POWERPC_EXCP_ALIGN_CACHE   = 0x06,  /* Impossible dcbz access            */    /* Exception subtypes for POWERPC_EXCP_PROGRAM                           */    /* FP exceptions                                                         */    POWERPC_EXCP_FP            = 0x10,    POWERPC_EXCP_FP_OX         = 0x01,  /* FP overflow                       */    POWERPC_EXCP_FP_UX         = 0x02,  /* FP underflow                      */    POWERPC_EXCP_FP_ZX         = 0x03,  /* FP divide by zero                 */    POWERPC_EXCP_FP_XX         = 0x04,  /* FP inexact                        */    POWERPC_EXCP_FP_VXSNAN     = 0x05,  /* FP invalid SNaN op                */    POWERPC_EXCP_FP_VXISI      = 0x06,  /* FP invalid infinite subtraction   */    POWERPC_EXCP_FP_VXIDI      = 0x07,  /* FP invalid infinite divide        */    POWERPC_EXCP_FP_VXZDZ      = 0x08,  /* FP invalid zero divide            */    POWERPC_EXCP_FP_VXIMZ      = 0x09,  /* FP invalid infinite * zero        */    POWERPC_EXCP_FP_VXVC       = 0x0A,  /* FP invalid compare                */    POWERPC_EXCP_FP_VXSOFT     = 0x0B,  /* FP invalid operation              */    POWERPC_EXCP_FP_VXSQRT     = 0x0C,  /* FP invalid square root            */    POWERPC_EXCP_FP_VXCVI      = 0x0D,  /* FP invalid integer conversion     */    /* Invalid instruction                                                   */    POWERPC_EXCP_INVAL         = 0x20,    POWERPC_EXCP_INVAL_INVAL   = 0x01,  /* Invalid instruction               */    POWERPC_EXCP_INVAL_LSWX    = 0x02,  /* Invalid lswx instruction          */    POWERPC_EXCP_INVAL_SPR     = 0x03,  /* Invalid SPR access                */    POWERPC_EXCP_INVAL_FP      = 0x04,  /* Unimplemented mandatory fp instr  */    /* Privileged instruction                                                */    POWERPC_EXCP_PRIV          = 0x30,    POWERPC_EXCP_PRIV_OPC      = 0x01,  /* Privileged operation exception    */    POWERPC_EXCP_PRIV_REG      = 0x02,  /* Privileged register exception     */    /* Trap                                                                  */    POWERPC_EXCP_TRAP          = 0x40,};/*****************************************************************************//* Input pins model                                                          */typedef enum powerpc_input_t powerpc_input_t;enum powerpc_input_t {    PPC_FLAGS_INPUT_UNKNOWN = 0,    /* PowerPC 6xx bus                  */    PPC_FLAGS_INPUT_6xx,    /* BookE bus                        */    PPC_FLAGS_INPUT_BookE,    /* PowerPC 405 bus                  */    PPC_FLAGS_INPUT_405,    /* PowerPC 970 bus                  */    PPC_FLAGS_INPUT_970,    /* PowerPC 401 bus                  */    PPC_FLAGS_INPUT_401,    /* Freescale RCPU bus               */    PPC_FLAGS_INPUT_RCPU,};#define PPC_INPUT(env) (env->bus_model)/*****************************************************************************/typedef struct ppc_def_t ppc_def_t;typedef struct opc_handler_t opc_handler_t;/*****************************************************************************//* Types used to describe some PowerPC registers */typedef struct CPUPPCState CPUPPCState;typedef struct ppc_tb_t ppc_tb_t;typedef struct ppc_spr_t ppc_spr_t;typedef struct ppc_dcr_t ppc_dcr_t;typedef union ppc_avr_t ppc_avr_t;typedef union ppc_tlb_t ppc_tlb_t;/* SPR access micro-ops generations callbacks */struct ppc_spr_t {    void (*uea_read)(void *opaque, int spr_num);    void (*uea_write)(void *opaque, int spr_num);#if !defined(CONFIG_USER_ONLY)    void (*oea_read)(void *opaque, int spr_num);    void (*oea_write)(void *opaque, int spr_num);    void (*hea_read)(void *opaque, int spr_num);    void (*hea_write)(void *opaque, int spr_num);#endif    const unsigned char *name;};/* Altivec registers (128 bits) */union ppc_avr_t {    uint8_t u8[16];    uint16_t u16[8];    uint32_t u32[4];    uint64_t u64[2];};/* Software TLB cache */typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;struct ppc6xx_tlb_t {    target_ulong pte0;    target_ulong pte1;    target_ulong EPN;};typedef struct ppcemb_tlb_t ppcemb_tlb_t;struct ppcemb_tlb_t {    target_phys_addr_t RPN;    target_ulong EPN;    target_ulong PID;    target_ulong size;    uint32_t prot;    uint32_t attr; /* Storage attributes */};union ppc_tlb_t {    ppc6xx_tlb_t tlb6;    ppcemb_tlb_t tlbe;};/*****************************************************************************//* Machine state register bits definition                                    */#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */#define MSR_TAG  62 /* Tag-active mode (POWERx ?)                            */#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */