#define MSR_SHV  60 /* hypervisor state                               hflags */#define MSR_CM   31 /* Computation mode for BookE                     hflags */#define MSR_ICM  30 /* Interrupt computation mode for BookE                  */#define MSR_THV  29 /* hypervisor state for 32 bits PowerPC           hflags */#define MSR_UCLE 26 /* User-mode cache lock enable for BookE                 */#define MSR_VR   25 /* altivec available                            x hflags */#define MSR_SPE  25 /* SPE enable for BookE                         x hflags */#define MSR_AP   23 /* Access privilege state on 602                  hflags */#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */#define MSR_KEY  19 /* key bit on 603e                                       */#define MSR_POW  18 /* Power management                                      */#define MSR_TGPR 17 /* TGPR usage on 602/603                        x        */#define MSR_CE   17 /* Critical interrupt enable on embedded PowerPC x       */#define MSR_ILE  16 /* Interrupt little-endian mode                          */#define MSR_EE   15 /* External interrupt enable                             */#define MSR_PR   14 /* Problem state                                  hflags */#define MSR_FP   13 /* Floating point available                       hflags */#define MSR_ME   12 /* Machine check interrupt enable                        */#define MSR_FE0  11 /* Floating point exception mode 0                hflags */#define MSR_SE   10 /* Single-step trace enable                     x hflags */#define MSR_DWE  10 /* Debug wait enable on 405                     x        */#define MSR_UBLE 10 /* User BTB lock enable on e500                 x        */#define MSR_BE   9  /* Branch trace enable                          x hflags */#define MSR_DE   9  /* Debug interrupts enable on embedded PowerPC  x        */#define MSR_FE1  8  /* Floating point exception mode 1                hflags */#define MSR_AL   7  /* AL bit on POWER                                       */#define MSR_EP   6  /* Exception prefix on 601                               */#define MSR_IR   5  /* Instruction relocate                                  */#define MSR_DR   4  /* Data relocate                                         */#define MSR_PE   3  /* Protection enable on 403                              */#define MSR_PX   2  /* Protection exclusive on 403                  x        */#define MSR_PMM  2  /* Performance monitor mark on POWER            x        */#define MSR_RI   1  /* Recoverable interrupt                        1        */#define MSR_LE   0  /* Little-endian mode                           1 hflags */#define msr_sf   ((env->msr >> MSR_SF)   & 1)#define msr_isf  ((env->msr >> MSR_ISF)  & 1)#define msr_shv  ((env->msr >> MSR_SHV)  & 1)#define msr_cm   ((env->msr >> MSR_CM)   & 1)#define msr_icm  ((env->msr >> MSR_ICM)  & 1)#define msr_thv  ((env->msr >> MSR_THV)  & 1)#define msr_ucle ((env->msr >> MSR_UCLE) & 1)#define msr_vr   ((env->msr >> MSR_VR)   & 1)#define msr_spe  ((env->msr >> MSR_SE)   & 1)#define msr_ap   ((env->msr >> MSR_AP)   & 1)#define msr_sa   ((env->msr >> MSR_SA)   & 1)#define msr_key  ((env->msr >> MSR_KEY)  & 1)#define msr_pow  ((env->msr >> MSR_POW)  & 1)#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)#define msr_ce   ((env->msr >> MSR_CE)   & 1)#define msr_ile  ((env->msr >> MSR_ILE)  & 1)#define msr_ee   ((env->msr >> MSR_EE)   & 1)#define msr_pr   ((env->msr >> MSR_PR)   & 1)#define msr_fp   ((env->msr >> MSR_FP)   & 1)#define msr_me   ((env->msr >> MSR_ME)   & 1)#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)#define msr_se   ((env->msr >> MSR_SE)   & 1)#define msr_dwe  ((env->msr >> MSR_DWE)  & 1)#define msr_uble ((env->msr >> MSR_UBLE) & 1)#define msr_be   ((env->msr >> MSR_BE)   & 1)#define msr_de   ((env->msr >> MSR_DE)   & 1)#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)#define msr_al   ((env->msr >> MSR_AL)   & 1)#define msr_ep   ((env->msr >> MSR_EP)   & 1)#define msr_ir   ((env->msr >> MSR_IR)   & 1)#define msr_dr   ((env->msr >> MSR_DR)   & 1)#define msr_pe   ((env->msr >> MSR_PE)   & 1)#define msr_px   ((env->msr >> MSR_PX)   & 1)#define msr_pmm  ((env->msr >> MSR_PMM)  & 1)#define msr_ri   ((env->msr >> MSR_RI)   & 1)#define msr_le   ((env->msr >> MSR_LE)   & 1)/* Hypervisor bit is more specific */#if defined(TARGET_PPC64)#define MSR_HVB (1ULL << MSR_SHV)#define msr_hv  msr_shv#else#if defined(PPC_EMULATE_32BITS_HYPV)#define MSR_HVB (1ULL << MSR_THV)#define msr_hv  msr_thv#else#define MSR_HVB (0ULL)#define msr_hv  (0)#endif#endifenum {    POWERPC_FLAG_NONE     = 0x00000000,    /* Flag for MSR bit 25 signification (VRE/SPE)                           */    POWERPC_FLAG_SPE      = 0x00000001,    POWERPC_FLAG_VRE      = 0x00000002,    /* Flag for MSR bit 17 signification (TGPR/CE)                           */    POWERPC_FLAG_TGPR     = 0x00000004,    POWERPC_FLAG_CE       = 0x00000008,    /* Flag for MSR bit 10 signification (SE/DWE/UBLE)                       */    POWERPC_FLAG_SE       = 0x00000010,    POWERPC_FLAG_DWE      = 0x00000020,    POWERPC_FLAG_UBLE     = 0x00000040,    /* Flag for MSR bit 9 signification (BE/DE)                              */    POWERPC_FLAG_BE       = 0x00000080,    POWERPC_FLAG_DE       = 0x00000100,    /* Flag for MSR bit 2 signification (PX/PMM)                             */    POWERPC_FLAG_PX       = 0x00000200,    POWERPC_FLAG_PMM      = 0x00000400,    /* Flag for special features                                             */    /* Decrementer clock: RTC clock (POWER, 601) or bus clock                */    POWERPC_FLAG_RTC_CLK  = 0x00010000,    POWERPC_FLAG_BUS_CLK  = 0x00020000,};/*****************************************************************************//* Floating point status and control register                                */#define FPSCR_FX     31 /* Floating-point exception summary                  */#define FPSCR_FEX    30 /* Floating-point enabled exception summary          */#define FPSCR_VX     29 /* Floating-point invalid operation exception summ.  */#define FPSCR_OX     28 /* Floating-point overflow exception                 */#define FPSCR_UX     27 /* Floating-point underflow exception                */#define FPSCR_ZX     26 /* Floating-point zero divide exception              */#define FPSCR_XX     25 /* Floating-point inexact exception                  */#define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */#define FPSCR_VXISI  23 /* Floating-point invalid operation exception (inf)  */#define FPSCR_VXIDI  22 /* Floating-point invalid operation exception (inf)  */#define FPSCR_VXZDZ  21 /* Floating-point invalid operation exception (zero) */#define FPSCR_VXIMZ  20 /* Floating-point invalid operation exception (inf)  */#define FPSCR_VXVC   19 /* Floating-point invalid operation exception (comp) */#define FPSCR_FR     18 /* Floating-point fraction rounded                   */#define FPSCR_FI     17 /* Floating-point fraction inexact                   */#define FPSCR_C      16 /* Floating-point result class descriptor            */#define FPSCR_FL     15 /* Floating-point less than or negative              */#define FPSCR_FG     14 /* Floating-point greater than or negative           */#define FPSCR_FE     13 /* Floating-point equal or zero                      */#define FPSCR_FU     12 /* Floating-point unordered or NaN                   */#define FPSCR_FPCC   12 /* Floating-point condition code                     */#define FPSCR_FPRF   12 /* Floating-point result flags                       */#define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */#define FPSCR_VXSQRT 9  /* Floating-point invalid operation exception (sqrt) */#define FPSCR_VXCVI  8  /* Floating-point invalid operation exception (int)  */#define FPSCR_VE     7  /* Floating-point invalid operation exception enable */#define FPSCR_OE     6  /* Floating-point overflow exception enable          */#define FPSCR_UE     5  /* Floating-point undeflow exception enable          */#define FPSCR_ZE     4  /* Floating-point zero divide exception enable       */#define FPSCR_XE     3  /* Floating-point inexact exception enable           */#define FPSCR_NI     2  /* Floating-point non-IEEE mode                      */#define FPSCR_RN1    1#define FPSCR_RN     0  /* Floating-point rounding control                   */#define fpscr_fex    (((env->fpscr) >> FPSCR_FEX)    & 0x1)#define fpscr_vx     (((env->fpscr) >> FPSCR_VX)     & 0x1)#define fpscr_ox     (((env->fpscr) >> FPSCR_OX)     & 0x1)#define fpscr_ux     (((env->fpscr) >> FPSCR_UX)     & 0x1)#define fpscr_zx     (((env->fpscr) >> FPSCR_ZX)     & 0x1)#define fpscr_xx     (((env->fpscr) >> FPSCR_XX)     & 0x1)#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)#define fpscr_vxisi  (((env->fpscr) >> FPSCR_VXISI)  & 0x1)#define fpscr_vxidi  (((env->fpscr) >> FPSCR_VXIDI)  & 0x1)#define fpscr_vxzdz  (((env->fpscr) >> FPSCR_VXZDZ)  & 0x1)#define fpscr_vximz  (((env->fpscr) >> FPSCR_VXIMZ)  & 0x1)#define fpscr_vxvc   (((env->fpscr) >> FPSCR_VXVC)   & 0x1)#define fpscr_fpcc   (((env->fpscr) >> FPSCR_FPCC)   & 0xF)#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)#define fpscr_vxcvi  (((env->fpscr) >> FPSCR_VXCVI)  & 0x1)#define fpscr_ve     (((env->fpscr) >> FPSCR_VE)     & 0x1)#define fpscr_oe     (((env->fpscr) >> FPSCR_OE)     & 0x1)#define fpscr_ue     (((env->fpscr) >> FPSCR_UE)     & 0x1)#define fpscr_ze     (((env->fpscr) >> FPSCR_ZE)     & 0x1)#define fpscr_xe     (((env->fpscr) >> FPSCR_XE)     & 0x1)#define fpscr_ni     (((env->fpscr) >> FPSCR_NI)     & 0x1)#define fpscr_rn     (((env->fpscr) >> FPSCR_RN)     & 0x3)/* Invalid operation exception summary */#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI)  | \                                  (1 << FPSCR_VXIDI)  | (1 << FPSCR_VXZDZ)  | \                                  (1 << FPSCR_VXIMZ)  | (1 << FPSCR_VXVC)   | \                                  (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \                                  (1 << FPSCR_VXCVI)))/* exception summary */#define fpscr_ex  (((env->fpscr) >> FPSCR_XX) & 0x1F)/* enabled exception summary */#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) &  \                   0x1F)/*****************************************************************************//* The whole PowerPC CPU context */#define NB_MMU_MODES 3struct CPUPPCState {    /* First are the most commonly used resources     * during translated code execution     */#if (HOST_LONG_BITS == 32)    /* temporary fixed-point registers     * used to emulate 64 bits registers on 32 bits hosts     */    uint64_t t0, t1, t2;#endif    ppc_avr_t avr0, avr1, avr2;    /* general purpose registers */    ppc_gpr_t gpr[32];#if !defined(TARGET_PPC64)    /* Storage for GPR MSB, used by the SPE extension */    ppc_gpr_t gprh[32];#endif    /* LR */    target_ulong lr;    /* CTR */    target_ulong ctr;    /* condition register */    uint8_t crf[8];    /* XER */    /* XXX: We use only 5 fields, but we want to keep the structure aligned */    uint8_t xer[8];    /* Reservation address */    target_ulong reserve;    /* Those ones are used in supervisor mode only */    /* machine state register */    target_ulong msr;    /* temporary general purpose registers */    ppc_gpr_t tgpr[4]; /* Used to speed-up TLB assist handlers */    /* Floating point execution context */    /* temporary float registers */    float64 ft0;    float64 ft1;    float64 ft2;    float_status fp_status;    /* floating point registers */    float64 fpr[32];    /* floating point status and control register */    uint32_t fpscr;    CPU_COMMON    int halted; /* TRUE if the CPU is in suspend state */    int access_type; /* when a memory exception occurs, the access                        type is stored here */    /* MMU context - only relevant for full system emulation */#if !defined(CONFIG_USER_ONLY)#if defined(TARGET_PPC64)    /* Address space register */    target_ulong asr;    /* PowerPC 64 SLB area */    int slb_nr;#endif    /* segment registers */    target_ulong sdr1;    target_ulong sr[16];    /* BATs */    int nb_BATs;    target_ulong DBAT[2][8];    target_ulong IBAT[2][8];    /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */    int nb_tlb;      /* Total number of TLB                                  */    int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */    int nb_ways;     /* Number of ways in the TLB set                        */    int last_way;    /* Last used way used to allocate TLB in a LRU way      */    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */    int nb_pids;     /* Number of available PID registers                    */    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */    /* 403 dedicated access protection registers */    target_ulong pb[4];#endif    /* Other registers */    /* Special purpose registers */    target_ulong spr[1024];    ppc_spr_t spr_cb[1024];    /* Altivec registers */    ppc_avr_t avr[32];    uint32_t vscr;    /* SPE registers */    ppc_gpr_t spe_acc;    float_status spe_status;    uint32_t spe_fscr;    /* Internal devices resources */    /* Time base and decrementer */    ppc_tb_t *tb_env;    /* Device control registers */    ppc_dcr_t *dcr_env;    int dcache_line_size;    int icache_line_size;    /* Those resources are used during exception processing */    /* CPU model definition */    target_ulong msr_mask;    powerpc_mmu_t mmu_model;    powerpc_excp_t excp_model;    powerpc_input_t bus_model;    int bfd_mach;    uint32_t flags;    int exception_index;    int error_code;    int interrupt_request;    uint32_t pending_interrupts;#if !defined(CONFIG_USER_ONLY)    /* This is the IRQ controller, which is implementation dependant     * and only relevant when emulating a complete machine.     */    uint32_t irq_input_state;    void **irq_inputs;    /* Exception vectors */    target_ulong excp_vectors[POWERPC_EXCP_NB];    target_ulong excp_prefix;    target_ulong ivor_mask;    target_ulong ivpr_mask;    target_ulong hreset_vector;#endif    /* Those resources are used only during code translation */    /* Next instruction pointer */    target_ulong nip;    /* opcode handlers */    opc_handler_t *opcodes[0x40];    /* Those resources are used only in Qemu core */    jmp_buf jmp_env;    int user_mode_only; /* user mode only simulation */    target_ulong hflags;      /* hflags is a MSR & HFLAGS_MASK         */    target_ulong hflags_nmsr; /* specific hflags, not comming from MSR */    int mmu_idx;         /* precomputed MMU index to speed up mem accesses */    /* Power management */    int power_mode;    int (*check_pow)(CPUPPCState *env);    /* temporary hack to handle OSI calls (only used if non NULL) */    int (*osi_call)(struct CPUPPCState *env);};/* Context used internally during MMU translations */typedef struct mmu_ctx_t mmu_ctx_t;struct mmu_ctx_t {    target_phys_addr_t raddr;      /* Real address              */    int prot;                      /* Protection bits           */    target_phys_addr_t pg_addr[2]; /* PTE tables base addresses */    target_ulong ptem;             /* Virtual segment ID | API  */    int key;                       /* Access key                */    int nx;                        /* Non-execute area          */};/*****************************************************************************/CPUPPCState *cpu_ppc_init (const char *cpu_model);int cpu_ppc_exec (CPUPPCState *s);void cpu_ppc_close (CPUPPCState *s);/* you can call this signal handler from your SIGBUS and SIGSEGV   signal handlers to inform the virtual CPU of exceptions. non zero   is returned if the signal was handled by the virtual CPU.  */int cpu_ppc_signal_handler (int host_signum, void *pinfo,                            void *puc);void do_interrupt (CPUPPCState *env);