/* *  PowerPC emulation for qemu: main translation routines. * *  Copyright (c) 2003-2007 Jocelyn Mayer * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */#include <stdarg.h>#include <stdlib.h>#include <stdio.h>#include <string.h>#include <inttypes.h>#include "cpu.h"#include "exec-all.h"#include "disas.h"/* Include definitions for instructions classes and implementations flags *///#define DO_SINGLE_STEP//#define PPC_DEBUG_DISAS//#define DEBUG_MEMORY_ACCESSES//#define DO_PPC_STATISTICS//#define OPTIMIZE_FPRF_UPDATE/*****************************************************************************//* Code translation helpers                                                  */#if defined(USE_DIRECT_JUMP)#define TBPARAM(x)#else#define TBPARAM(x) (long)(x)#endifenum {#define DEF(s, n, copy_size) INDEX_op_ ## s,#include "opc.h"#undef DEF    NB_OPS,};static uint16_t *gen_opc_ptr;static uint32_t *gen_opparam_ptr;#if defined(OPTIMIZE_FPRF_UPDATE)static uint16_t *gen_fprf_buf[OPC_BUF_SIZE];static uint16_t **gen_fprf_ptr;#endif#include "gen-op.h"static always_inline void gen_set_T0 (target_ulong val){#if defined(TARGET_PPC64)    if (val >> 32)        gen_op_set_T0_64(val >> 32, val);    else#endif        gen_op_set_T0(val);}static always_inline void gen_set_T1 (target_ulong val){#if defined(TARGET_PPC64)    if (val >> 32)        gen_op_set_T1_64(val >> 32, val);    else#endif        gen_op_set_T1(val);}#define GEN8(func, NAME)                                                      \static GenOpFunc *NAME ## _table [8] = {                                      \NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \};                                                                            \static always_inline void func (int n)                                        \{                                                                             \    NAME ## _table[n]();                                                      \}#define GEN16(func, NAME)                                                     \static GenOpFunc *NAME ## _table [16] = {                                     \NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \};                                                                            \static always_inline void func (int n)                                        \{                                                                             \    NAME ## _table[n]();                                                      \}#define GEN32(func, NAME)                                                     \static GenOpFunc *NAME ## _table [32] = {                                     \NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \};                                                                            \static always_inline void func (int n)                                        \{                                                                             \    NAME ## _table[n]();                                                      \}/* Condition register moves */GEN8(gen_op_load_crf_T0, gen_op_load_crf_T0_crf);GEN8(gen_op_load_crf_T1, gen_op_load_crf_T1_crf);GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);#if 0 // UnusedGEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);#endif/* General purpose registers moves */GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);#if 0 // unusedGEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);#endif/* floating point registers moves */GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);GEN32(gen_op_load_fpr_FT2, gen_op_load_fpr_FT2_fpr);GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fpr);GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fpr);#if 0 // unusedGEN32(gen_op_store_FT2_fpr, gen_op_store_FT2_fpr_fpr);#endif/* internal defines */typedef struct DisasContext {    struct TranslationBlock *tb;    target_ulong nip;    uint32_t opcode;    uint32_t exception;    /* Routine used to access memory */    int mem_idx;    /* Translation flags */#if !defined(CONFIG_USER_ONLY)    int supervisor;#endif#if defined(TARGET_PPC64)    int sf_mode;#endif    int fpu_enabled;    int altivec_enabled;    int spe_enabled;    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */    int singlestep_enabled;    int dcache_line_size;} DisasContext;struct opc_handler_t {    /* invalid bits */    uint32_t inval;    /* instruction type */    uint64_t type;    /* handler */    void (*handler)(DisasContext *ctx);#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)    const unsigned char *oname;#endif#if defined(DO_PPC_STATISTICS)    uint64_t count;#endif};static always_inline void gen_set_Rc0 (DisasContext *ctx){#if defined(TARGET_PPC64)    if (ctx->sf_mode)        gen_op_cmpi_64(0);    else#endif        gen_op_cmpi(0);    gen_op_set_Rc0();}static always_inline void gen_reset_fpstatus (void){#ifdef CONFIG_SOFTFLOAT    gen_op_reset_fpstatus();#endif}static always_inline void gen_compute_fprf (int set_fprf, int set_rc){    if (set_fprf != 0) {        /* This case might be optimized later */#if defined(OPTIMIZE_FPRF_UPDATE)        *gen_fprf_ptr++ = gen_opc_ptr;#endif        gen_op_compute_fprf(1);        if (unlikely(set_rc))            gen_op_store_T0_crf(1);        gen_op_float_check_status();    } else if (unlikely(set_rc)) {        /* We always need to compute fpcc */        gen_op_compute_fprf(0);        gen_op_store_T0_crf(1);        if (set_fprf)            gen_op_float_check_status();    }}static always_inline void gen_optimize_fprf (void){#if defined(OPTIMIZE_FPRF_UPDATE)    uint16_t **ptr;    for (ptr = gen_fprf_buf; ptr != (gen_fprf_ptr - 1); ptr++)        *ptr = INDEX_op_nop1;    gen_fprf_ptr = gen_fprf_buf;#endif}static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip){#if defined(TARGET_PPC64)    if (ctx->sf_mode)        gen_op_update_nip_64(nip >> 32, nip);    else#endif        gen_op_update_nip(nip);}#define GEN_EXCP(ctx, excp, error)                                            \do {                                                                          \    if ((ctx)->exception == POWERPC_EXCP_NONE) {                              \        gen_update_nip(ctx, (ctx)->nip);                                      \    }                                                                         \    gen_op_raise_exception_err((excp), (error));                              \    ctx->exception = (excp);                                                  \} while (0)#define GEN_EXCP_INVAL(ctx)                                                   \GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \         POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL)#define GEN_EXCP_PRIVOPC(ctx)                                                 \GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_OPC)#define GEN_EXCP_PRIVREG(ctx)                                                 \GEN_EXCP((ctx), POWERPC_EXCP_PROGRAM,                                         \         POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG)#define GEN_EXCP_NO_FP(ctx)                                                   \GEN_EXCP(ctx, POWERPC_EXCP_FPU, 0)#define GEN_EXCP_NO_AP(ctx)                                                   \GEN_EXCP(ctx, POWERPC_EXCP_APU, 0)#define GEN_EXCP_NO_VR(ctx)                                                   \GEN_EXCP(ctx, POWERPC_EXCP_VPU, 0)/* Stop translation */static always_inline void GEN_STOP (DisasContext *ctx){    gen_update_nip(ctx, ctx->nip);    ctx->exception = POWERPC_EXCP_STOP;}/* No need to update nip here, as execution flow will change */static always_inline void GEN_SYNC (DisasContext *ctx){    ctx->exception = POWERPC_EXCP_SYNC;}#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \static void gen_##name (DisasContext *ctx);                                   \GEN_OPCODE(name, opc1, opc2, opc3, inval, type);                              \static void gen_##name (DisasContext *ctx)#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \static void gen_##name (DisasContext *ctx);                                   \GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type);                       \static void gen_##name (DisasContext *ctx)typedef struct opcode_t {    unsigned char opc1, opc2, opc3;#if HOST_LONG_BITS == 64 /* Explicitely align to 64 bits */    unsigned char pad[5];#else    unsigned char pad[1];#endif    opc_handler_t handler;    const unsigned char *oname;} opcode_t;/*****************************************************************************//***                           Instruction decoding                        ***/#define EXTRACT_HELPER(name, shift, nb)                                       \static always_inline uint32_t name (uint32_t opcode)                          \{                                                                             \    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \}#define EXTRACT_SHELPER(name, shift, nb)                                      \static always_inline int32_t name (uint32_t opcode)                           \{                                                                             \    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \}/* Opcode part 1 */EXTRACT_HELPER(opc1, 26, 6);/* Opcode part 2 */EXTRACT_HELPER(opc2, 1, 5);/* Opcode part 3 */EXTRACT_HELPER(opc3, 6, 5);/* Update Cr0 flags */EXTRACT_HELPER(Rc, 0, 1);/* Destination */EXTRACT_HELPER(rD, 21, 5);/* Source */EXTRACT_HELPER(rS, 21, 5);/* First operand */EXTRACT_HELPER(rA, 16, 5);/* Second operand */EXTRACT_HELPER(rB, 11, 5);/* Third operand */EXTRACT_HELPER(rC, 6, 5);/***                               Get CRn                                 ***/EXTRACT_HELPER(crfD, 23, 3);EXTRACT_HELPER(crfS, 18, 3);EXTRACT_HELPER(crbD, 21, 5);EXTRACT_HELPER(crbA, 16, 5);EXTRACT_HELPER(crbB, 11, 5);/* SPR / TBL */EXTRACT_HELPER(_SPR, 11, 10);static always_inline uint32_t SPR (uint32_t opcode)