static always_inline uint32_t _do_efsctuiz (uint32_t val){    union {        int32_t u;        float32 f;    } u;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    return float32_to_uint32_round_to_zero(u.f, &env->spe_status);}void do_efscfsi (void){    T0_64 = _do_efscfsi(T0_64);}void do_efscfui (void){    T0_64 = _do_efscfui(T0_64);}void do_efsctsi (void){    T0_64 = _do_efsctsi(T0_64);}void do_efsctui (void){    T0_64 = _do_efsctui(T0_64);}void do_efsctsiz (void){    T0_64 = _do_efsctsiz(T0_64);}void do_efsctuiz (void){    T0_64 = _do_efsctuiz(T0_64);}/* Single precision floating-point conversion to/from fractional */static always_inline uint32_t _do_efscfsf (uint32_t val){    union {        uint32_t u;        float32 f;    } u;    float32 tmp;    u.f = int32_to_float32(val, &env->spe_status);    tmp = int64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_div(u.f, tmp, &env->spe_status);    return u.u;}static always_inline uint32_t _do_efscfuf (uint32_t val){    union {        uint32_t u;        float32 f;    } u;    float32 tmp;    u.f = uint32_to_float32(val, &env->spe_status);    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_div(u.f, tmp, &env->spe_status);    return u.u;}static always_inline int32_t _do_efsctsf (uint32_t val){    union {        int32_t u;        float32 f;    } u;    float32 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_mul(u.f, tmp, &env->spe_status);    return float32_to_int32(u.f, &env->spe_status);}static always_inline uint32_t _do_efsctuf (uint32_t val){    union {        int32_t u;        float32 f;    } u;    float32 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_mul(u.f, tmp, &env->spe_status);    return float32_to_uint32(u.f, &env->spe_status);}static always_inline int32_t _do_efsctsfz (uint32_t val){    union {        int32_t u;        float32 f;    } u;    float32 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_mul(u.f, tmp, &env->spe_status);    return float32_to_int32_round_to_zero(u.f, &env->spe_status);}static always_inline uint32_t _do_efsctufz (uint32_t val){    union {        int32_t u;        float32 f;    } u;    float32 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float32(1ULL << 32, &env->spe_status);    u.f = float32_mul(u.f, tmp, &env->spe_status);    return float32_to_uint32_round_to_zero(u.f, &env->spe_status);}void do_efscfsf (void){    T0_64 = _do_efscfsf(T0_64);}void do_efscfuf (void){    T0_64 = _do_efscfuf(T0_64);}void do_efsctsf (void){    T0_64 = _do_efsctsf(T0_64);}void do_efsctuf (void){    T0_64 = _do_efsctuf(T0_64);}void do_efsctsfz (void){    T0_64 = _do_efsctsfz(T0_64);}void do_efsctufz (void){    T0_64 = _do_efsctufz(T0_64);}/* Double precision floating point helpers */static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2){    /* XXX: TODO: test special values (NaN, infinites, ...) */    return _do_efdtstlt(op1, op2);}static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2){    /* XXX: TODO: test special values (NaN, infinites, ...) */    return _do_efdtstgt(op1, op2);}static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2){    /* XXX: TODO: test special values (NaN, infinites, ...) */    return _do_efdtsteq(op1, op2);}void do_efdcmplt (void){    T0 = _do_efdcmplt(T0_64, T1_64);}void do_efdcmpgt (void){    T0 = _do_efdcmpgt(T0_64, T1_64);}void do_efdcmpeq (void){    T0 = _do_efdcmpeq(T0_64, T1_64);}/* Double precision floating-point conversion to/from integer */static always_inline uint64_t _do_efdcfsi (int64_t val){    union {        uint64_t u;        float64 f;    } u;    u.f = int64_to_float64(val, &env->spe_status);    return u.u;}static always_inline uint64_t _do_efdcfui (uint64_t val){    union {        uint64_t u;        float64 f;    } u;    u.f = uint64_to_float64(val, &env->spe_status);    return u.u;}static always_inline int64_t _do_efdctsi (uint64_t val){    union {        int64_t u;        float64 f;    } u;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    return float64_to_int64(u.f, &env->spe_status);}static always_inline uint64_t _do_efdctui (uint64_t val){    union {        int64_t u;        float64 f;    } u;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    return float64_to_uint64(u.f, &env->spe_status);}static always_inline int64_t _do_efdctsiz (uint64_t val){    union {        int64_t u;        float64 f;    } u;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    return float64_to_int64_round_to_zero(u.f, &env->spe_status);}static always_inline uint64_t _do_efdctuiz (uint64_t val){    union {        int64_t u;        float64 f;    } u;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    return float64_to_uint64_round_to_zero(u.f, &env->spe_status);}void do_efdcfsi (void){    T0_64 = _do_efdcfsi(T0_64);}void do_efdcfui (void){    T0_64 = _do_efdcfui(T0_64);}void do_efdctsi (void){    T0_64 = _do_efdctsi(T0_64);}void do_efdctui (void){    T0_64 = _do_efdctui(T0_64);}void do_efdctsiz (void){    T0_64 = _do_efdctsiz(T0_64);}void do_efdctuiz (void){    T0_64 = _do_efdctuiz(T0_64);}/* Double precision floating-point conversion to/from fractional */static always_inline uint64_t _do_efdcfsf (int64_t val){    union {        uint64_t u;        float64 f;    } u;    float64 tmp;    u.f = int32_to_float64(val, &env->spe_status);    tmp = int64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_div(u.f, tmp, &env->spe_status);    return u.u;}static always_inline uint64_t _do_efdcfuf (uint64_t val){    union {        uint64_t u;        float64 f;    } u;    float64 tmp;    u.f = uint32_to_float64(val, &env->spe_status);    tmp = int64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_div(u.f, tmp, &env->spe_status);    return u.u;}static always_inline int64_t _do_efdctsf (uint64_t val){    union {        int64_t u;        float64 f;    } u;    float64 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_mul(u.f, tmp, &env->spe_status);    return float64_to_int32(u.f, &env->spe_status);}static always_inline uint64_t _do_efdctuf (uint64_t val){    union {        int64_t u;        float64 f;    } u;    float64 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_mul(u.f, tmp, &env->spe_status);    return float64_to_uint32(u.f, &env->spe_status);}static always_inline int64_t _do_efdctsfz (uint64_t val){    union {        int64_t u;        float64 f;    } u;    float64 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_mul(u.f, tmp, &env->spe_status);    return float64_to_int32_round_to_zero(u.f, &env->spe_status);}static always_inline uint64_t _do_efdctufz (uint64_t val){    union {        int64_t u;        float64 f;    } u;    float64 tmp;    u.u = val;    /* NaN are not treated the same way IEEE 754 does */    if (unlikely(isnan(u.f)))        return 0;    tmp = uint64_to_float64(1ULL << 32, &env->spe_status);    u.f = float64_mul(u.f, tmp, &env->spe_status);    return float64_to_uint32_round_to_zero(u.f, &env->spe_status);}void do_efdcfsf (void){    T0_64 = _do_efdcfsf(T0_64);}void do_efdcfuf (void){    T0_64 = _do_efdcfuf(T0_64);}void do_efdctsf (void){    T0_64 = _do_efdctsf(T0_64);}void do_efdctuf (void){    T0_64 = _do_efdctuf(T0_64);}void do_efdctsfz (void){    T0_64 = _do_efdctsfz(T0_64);}void do_efdctufz (void){    T0_64 = _do_efdctufz(T0_64);}/* Floating point conversion between single and double precision */static always_inline uint32_t _do_efscfd (uint64_t val){    union {        uint64_t u;        float64 f;    } u1;    union {        uint32_t u;        float32 f;    } u2;    u1.u = val;    u2.f = float64_to_float32(u1.f, &env->spe_status);    return u2.u;}static always_inline uint64_t _do_efdcfs (uint32_t val){    union {        uint64_t u;        float64 f;    } u2;    union {        uint32_t u;        float32 f;    } u1;    u1.u = val;    u2.f = float32_to_float64(u1.f, &env->spe_status);    return u2.u;}void do_efscfd (void){    T0_64 = _do_efscfd(T0_64);}void do_efdcfs (void){    T0_64 = _do_efdcfs(T0_64);}/* Single precision fixed-point vector arithmetic *//* evfsabs */DO_SPE_OP1(fsabs);/* evfsnabs */DO_SPE_OP1(fsnabs);/* evfsneg */DO_SPE_OP1(fsneg);/* evfsadd */DO_SPE_OP2(fsadd);/* evfssub */DO_SPE_OP2(fssub);/* evfsmul */DO_SPE_OP2(fsmul);/* evfsdiv */DO_SPE_OP2(fsdiv);/* Single-precision floating-point comparisons */static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2){    /* XXX: TODO: test special values (NaN, infinites, ...) */    return _do_efststlt(op1, op