#include "exec.h"#include "host-utils.h"//#define DEBUG_PCALL//#define DEBUG_MMU//#define DEBUG_MXCC//#define DEBUG_UNALIGNED//#define DEBUG_UNASSIGNED//#define DEBUG_ASI#ifdef DEBUG_MMU#define DPRINTF_MMU(fmt, args...) \do { printf("MMU: " fmt , ##args); } while (0)#else#define DPRINTF_MMU(fmt, args...)#endif#ifdef DEBUG_MXCC#define DPRINTF_MXCC(fmt, args...) \do { printf("MXCC: " fmt , ##args); } while (0)#else#define DPRINTF_MXCC(fmt, args...)#endif#ifdef DEBUG_ASI#define DPRINTF_ASI(fmt, args...) \do { printf("ASI: " fmt , ##args); } while (0)#else#define DPRINTF_ASI(fmt, args...)#endifvoid raise_exception(int tt){    env->exception_index = tt;    cpu_loop_exit();}void check_ieee_exceptions(){     T0 = get_float_exception_flags(&env->fp_status);     if (T0)     {        /* Copy IEEE 754 flags into FSR */        if (T0 & float_flag_invalid)            env->fsr |= FSR_NVC;        if (T0 & float_flag_overflow)            env->fsr |= FSR_OFC;        if (T0 & float_flag_underflow)            env->fsr |= FSR_UFC;        if (T0 & float_flag_divbyzero)            env->fsr |= FSR_DZC;        if (T0 & float_flag_inexact)            env->fsr |= FSR_NXC;        if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23))        {            /* Unmasked exception, generate a trap */            env->fsr |= FSR_FTT_IEEE_EXCP;            raise_exception(TT_FP_EXCP);        }        else        {            /* Accumulate exceptions */            env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;        }     }}#ifdef USE_INT_TO_FLOAT_HELPERSvoid do_fitos(void){    set_float_exception_flags(0, &env->fp_status);    FT0 = int32_to_float32(*((int32_t *)&FT1), &env->fp_status);    check_ieee_exceptions();}void do_fitod(void){    DT0 = int32_to_float64(*((int32_t *)&FT1), &env->fp_status);}#if defined(CONFIG_USER_ONLY)void do_fitoq(void){    QT0 = int32_to_float128(*((int32_t *)&FT1), &env->fp_status);}#endif#ifdef TARGET_SPARC64void do_fxtos(void){    set_float_exception_flags(0, &env->fp_status);    FT0 = int64_to_float32(*((int64_t *)&DT1), &env->fp_status);    check_ieee_exceptions();}void do_fxtod(void){    set_float_exception_flags(0, &env->fp_status);    DT0 = int64_to_float64(*((int64_t *)&DT1), &env->fp_status);    check_ieee_exceptions();}#if defined(CONFIG_USER_ONLY)void do_fxtoq(void){    set_float_exception_flags(0, &env->fp_status);    QT0 = int64_to_float128(*((int32_t *)&DT1), &env->fp_status);    check_ieee_exceptions();}#endif#endif#endifvoid do_fabss(void){    FT0 = float32_abs(FT1);}#ifdef TARGET_SPARC64void do_fabsd(void){    DT0 = float64_abs(DT1);}#if defined(CONFIG_USER_ONLY)void do_fabsq(void){    QT0 = float128_abs(QT1);}#endif#endifvoid do_fsqrts(void){    set_float_exception_flags(0, &env->fp_status);    FT0 = float32_sqrt(FT1, &env->fp_status);    check_ieee_exceptions();}void do_fsqrtd(void){    set_float_exception_flags(0, &env->fp_status);    DT0 = float64_sqrt(DT1, &env->fp_status);    check_ieee_exceptions();}#if defined(CONFIG_USER_ONLY)void do_fsqrtq(void){    set_float_exception_flags(0, &env->fp_status);    QT0 = float128_sqrt(QT1, &env->fp_status);    check_ieee_exceptions();}#endif#define GEN_FCMP(name, size, reg1, reg2, FS, TRAP)                      \    void glue(do_, name) (void)                                         \    {                                                                   \        env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS);                     \        switch (glue(size, _compare) (reg1, reg2, &env->fp_status)) {   \        case float_relation_unordered:                                  \            T0 = (FSR_FCC1 | FSR_FCC0) << FS;                           \            if ((env->fsr & FSR_NVM) || TRAP) {                         \                env->fsr |= T0;                                         \                env->fsr |= FSR_NVC;                                    \                env->fsr |= FSR_FTT_IEEE_EXCP;                          \                raise_exception(TT_FP_EXCP);                            \            } else {                                                    \                env->fsr |= FSR_NVA;                                    \            }                                                           \            break;                                                      \        case float_relation_less:                                       \            T0 = FSR_FCC0 << FS;                                        \            break;                                                      \        case float_relation_greater:                                    \            T0 = FSR_FCC1 << FS;                                        \            break;                                                      \        default:                                                        \            T0 = 0;                                                     \            break;                                                      \        }                                                               \        env->fsr |= T0;                                                 \    }GEN_FCMP(fcmps, float32, FT0, FT1, 0, 0);GEN_FCMP(fcmpd, float64, DT0, DT1, 0, 0);GEN_FCMP(fcmpes, float32, FT0, FT1, 0, 1);GEN_FCMP(fcmped, float64, DT0, DT1, 0, 1);#ifdef CONFIG_USER_ONLYGEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);#endif#ifdef TARGET_SPARC64GEN_FCMP(fcmps_fcc1, float32, FT0, FT1, 22, 0);GEN_FCMP(fcmpd_fcc1, float64, DT0, DT1, 22, 0);GEN_FCMP(fcmps_fcc2, float32, FT0, FT1, 24, 0);GEN_FCMP(fcmpd_fcc2, float64, DT0, DT1, 24, 0);GEN_FCMP(fcmps_fcc3, float32, FT0, FT1, 26, 0);GEN_FCMP(fcmpd_fcc3, float64, DT0, DT1, 26, 0);GEN_FCMP(fcmpes_fcc1, float32, FT0, FT1, 22, 1);GEN_FCMP(fcmped_fcc1, float64, DT0, DT1, 22, 1);GEN_FCMP(fcmpes_fcc2, float32, FT0, FT1, 24, 1);GEN_FCMP(fcmped_fcc2, float64, DT0, DT1, 24, 1);GEN_FCMP(fcmpes_fcc3, float32, FT0, FT1, 26, 1);GEN_FCMP(fcmped_fcc3, float64, DT0, DT1, 26, 1);#ifdef CONFIG_USER_ONLYGEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);#endif#endif#ifndef TARGET_SPARC64#ifndef CONFIG_USER_ONLY#ifdef DEBUG_MXCCstatic void dump_mxcc(CPUState *env){    printf("mxccdata: %016llx %016llx %016llx %016llx\n",        env->mxccdata[0], env->mxccdata[1], env->mxccdata[2], env->mxccdata[3]);    printf("mxccregs: %016llx %016llx %016llx %016llx\n"           "          %016llx %016llx %016llx %016llx\n",        env->mxccregs[0], env->mxccregs[1], env->mxccregs[2], env->mxccregs[3],        env->mxccregs[4], env->mxccregs[5], env->mxccregs[6], env->mxccregs[7]);}#endif#ifdef DEBUG_ASIstatic void dump_asi(const char * txt, uint32_t addr, int asi, int size,                     uint32_t r1, uint32_t r2){    switch (size)    {    case 1:        DPRINTF_ASI("%s %08x asi 0x%02x = %02x\n", txt, addr, asi, r1 & 0xff);        break;    case 2:        DPRINTF_ASI("%s %08x asi 0x%02x = %04x\n", txt, addr, asi, r1 & 0xffff);        break;    case 4:        DPRINTF_ASI("%s %08x asi 0x%02x = %08x\n", txt, addr, asi, r1);        break;    case 8:        DPRINTF_ASI("%s %08x asi 0x%02x = %016llx\n", txt, addr, asi,                    r2 | ((uint64_t)r1 << 32));        break;    }}#endifvoid helper_ld_asi(int asi, int size, int sign){    uint32_t ret = 0;    uint64_t tmp;#if defined(DEBUG_MXCC) || defined(DEBUG_ASI)    uint32_t last_T0 = T0;#endif    switch (asi) {    case 2: /* SuperSparc MXCC registers */        switch (T0) {        case 0x01c00a00: /* MXCC control register */            if (size == 8) {                ret = env->mxccregs[3] >> 32;                T0 = env->mxccregs[3];            } else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00a04: /* MXCC control register */            if (size == 4)                ret = env->mxccregs[3];            else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00c00: /* Module reset register */            if (size == 8) {                ret = env->mxccregs[5] >> 32;                T0 = env->mxccregs[5];                // should we do something here?            } else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00f00: /* MBus port address register */            if (size == 8) {                ret = env->mxccregs[7] >> 32;                T0 = env->mxccregs[7];            } else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        default:            DPRINTF_MXCC("%08x: unimplemented address, size: %d\n", T0, size);            break;        }        DPRINTF_MXCC("asi = %d, size = %d, sign = %d, T0 = %08x -> ret = %08x,"                     "T0 = %08x\n", asi, size, sign, last_T0, ret, T0);#ifdef DEBUG_MXCC        dump_mxcc(env);#endif        break;    case 3: /* MMU probe */        {            int mmulev;            mmulev = (T0 >> 8) & 15;            if (mmulev > 4)                ret = 0;            else {                ret = mmu_probe(env, T0, mmulev);                //bswap32s(&ret);            }            DPRINTF_MMU("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);        }        break;    case 4: /* read MMU regs */        {            int reg = (T0 >> 8) & 0x1f;            ret = env->mmuregs[reg];            if (reg == 3) /* Fault status cleared on read */                env->mmuregs[3] = 0;            else if (reg == 0x13) /* Fault status read */                ret = env->mmuregs[3];            else if (reg == 0x14) /* Fault address read */                ret = env->mmuregs[4];            DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret);        }        break;    case 5: // Turbosparc ITLB Diagnostic    case 6: // Turbosparc DTLB Diagnostic    case 7: // Turbosparc IOTLB Diagnostic        break;    case 9: /* Supervisor code access */        switch(size) {        case 1:            ret = ldub_code(T0);            break;        case 2:            ret = lduw_code(T0 & ~1);            break;        default:        case 4:            ret = ldl_code(T0 & ~3);            break;        case 8:            tmp = ldq_code(T0 & ~7);            ret = tmp >> 32;            T0 = tmp;            break;        }        break;    case 0xa: /* User data access */        switch(size) {        case 1:            ret = ldub_user(T0);            break;        case 2:            ret = lduw_user(T0 & ~1);            break;        default:        case 4:            ret = ldl_user(T0 & ~3);            break;        case 8:            tmp = ldq_user(T0 & ~7);            ret = tmp >> 32;            T0 = tmp;            break;        }        break;    case 0xb: /* Supervisor data access */        switch(size) {        case 1:            ret = ldub_kernel(T0);            break;        case 2:            ret = lduw_kernel(T0 & ~1);            break;        default:        case 4:            ret = ldl_kernel(T0 & ~3);            break;        case 8:            tmp = ldq_kernel(T0 & ~7);            ret = tmp >> 32;            T0 = tmp;            break;        }        break;    case 0xc: /* I-cache tag */    case 0xd: /* I-cache data */    case 0xe: /* D-cache tag */    case 0xf: /* D-cache data */        break;    case 0x20: /* MMU passthrough */        switch(size) {        case 1:            ret = ldub_phys(T0);            break;        case 2:            ret = lduw_phys(T0 & ~1);            break;        default:        case 4:            ret = ldl_phys(T0 & ~3);            break;        case 8:            tmp = ldq_phys(T0 & ~7);            ret = tmp >> 32;            T0 = tmp;            break;        }        break;    case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */        switch(size) {        case 1:            ret = ldub_phys((target_phys_addr_t)T0                            | ((target_phys_addr_t)(asi & 0xf) << 32));            break;        case 2:            ret = lduw_phys((target_phys_addr_t)(T0 & ~1)                            | ((target_phys_addr_t)(asi & 0xf) << 32));            break;        default:        case 4:            ret = ldl_phys((target_phys_addr_t)(T0 & ~3)                           | ((target_phys_addr_t)(asi & 0xf) << 32));            break;        case 8:            tmp = ldq_phys((target_phys_addr_t)(T0 & ~7)                           | ((target_phys_addr_t)(asi & 0xf) << 32));            ret = tmp >> 32;            T0 = tmp;            break;        }        break;    case 0x30: // Turbosparc secondary cache diagnostic    case 0x31: // Turbosparc RAM snoop    case 0x32: // Turbosparc page table descriptor diagnostic    case 0x39: /* data cache diagnostic register */        ret = 0;        break;    case 8: /* User code access, XXX */    default:        do_unassigned_access(T0, 0, 0, asi);        ret = 0;        break;    }    if (sign) {        switch(size) {        case 1:            T1 = (int8_t) ret;            break;        case 2:            T1 = (int16_t) ret;            break;        default:            T1 = ret;            break;        }    }    else        T1 = ret;#ifdef DEBUG_ASI    dump_asi("read ", last_T0, asi, size, T1, T0);#endif}void helper_st_asi(int asi, int size){    switch(asi) {    case 2: /* SuperSparc MXCC registers */        switch (T0) {        case 0x01c00000: /* MXCC stream data register 0 */            if (size == 8)                env->mxccdata[0] = ((uint64_t)T1 << 32) | T2;            else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00008: /* MXCC stream data register 1 */            if (size == 8)                env->mxccdata[1] = ((uint64_t)T1 << 32) | T2;            else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00010: /* MXCC stream data register 2 */            if (size == 8)                env->mxccdata[2] = ((uint64_t)T1 << 32) | T2;            else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00018: /* MXCC stream data register 3 */            if (size == 8)                env->mxccdata[3] = ((uint64_t)T1 << 32) | T2;            else                DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size);            break;        case 0x01c00100: /* MXCC stream source */