/* Disassemble SH instructions.   Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004   Free Software Foundation, Inc.   This program is free software; you can redistribute it and/or modify   it under the terms of the GNU General Public License as published by   the Free Software Foundation; either version 2 of the License, or   (at your option) any later version.   This program is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the   GNU General Public License for more details.   You should have received a copy of the GNU General Public License   along with this program; if not, write to the Free Software   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */#include <stdio.h>#include "dis-asm.h"#define DEFINE_TABLEtypedef enum  {    HEX_0,    HEX_1,    HEX_2,    HEX_3,    HEX_4,    HEX_5,    HEX_6,    HEX_7,    HEX_8,    HEX_9,    HEX_A,    HEX_B,    HEX_C,    HEX_D,    HEX_E,    HEX_F,    HEX_XX00,    HEX_00YY,    REG_N,    REG_N_D,     /* nnn0 */    REG_N_B01,   /* nn01 */    REG_M,    SDT_REG_N,    REG_NM,    REG_B,    BRANCH_12,    BRANCH_8,    IMM0_4,    IMM0_4BY2,    IMM0_4BY4,    IMM1_4,    IMM1_4BY2,    IMM1_4BY4,    PCRELIMM_8BY2,    PCRELIMM_8BY4,    IMM0_8,    IMM0_8BY2,    IMM0_8BY4,    IMM1_8,    IMM1_8BY2,    IMM1_8BY4,    PPI,    NOPX,    NOPY,    MOVX,    MOVY,    MOVX_NOPY,    MOVY_NOPX,    PSH,    PMUL,    PPI3,    PPI3NC,    PDC,    PPIC,    REPEAT,    IMM0_3c,	/* xxxx 0iii */    IMM0_3s,	/* xxxx 1iii */    IMM0_3Uc,	/* 0iii xxxx */    IMM0_3Us,	/* 1iii xxxx */    IMM0_20_4,    IMM0_20,	/* follows IMM0_20_4 */    IMM0_20BY8,	/* follows IMM0_20_4 */    DISP0_12,    DISP0_12BY2,    DISP0_12BY4,    DISP0_12BY8,    DISP1_12,    DISP1_12BY2,    DISP1_12BY4,    DISP1_12BY8  }sh_nibble_type;typedef enum  {    A_END,    A_BDISP12,    A_BDISP8,    A_DEC_M,    A_DEC_N,    A_DISP_GBR,    A_PC,    A_DISP_PC,    A_DISP_PC_ABS,    A_DISP_REG_M,    A_DISP_REG_N,    A_GBR,    A_IMM,    A_INC_M,    A_INC_N,    A_IND_M,    A_IND_N,    A_IND_R0_REG_M,    A_IND_R0_REG_N,    A_MACH,    A_MACL,    A_PR,    A_R0,    A_R0_GBR,    A_REG_M,    A_REG_N,    A_REG_B,    A_SR,    A_VBR,    A_TBR,    A_DISP_TBR,    A_DISP2_TBR,    A_DEC_R15,    A_INC_R15,    A_MOD,    A_RE,    A_RS,    A_DSR,    DSP_REG_M,    DSP_REG_N,    DSP_REG_X,    DSP_REG_Y,    DSP_REG_E,    DSP_REG_F,    DSP_REG_G,    DSP_REG_A_M,    DSP_REG_AX,    DSP_REG_XY,    DSP_REG_AY,    DSP_REG_YX,    AX_INC_N,    AY_INC_N,    AXY_INC_N,    AYX_INC_N,    AX_IND_N,    AY_IND_N,    AXY_IND_N,    AYX_IND_N,    AX_PMOD_N,    AXY_PMOD_N,    AY_PMOD_N,    AYX_PMOD_N,    AS_DEC_N,    AS_INC_N,    AS_IND_N,    AS_PMOD_N,    A_A0,    A_X0,    A_X1,    A_Y0,    A_Y1,    A_SSR,    A_SPC,    A_SGR,    A_DBR,    F_REG_N,    F_REG_M,    D_REG_N,    D_REG_M,    X_REG_N, /* Only used for argument parsing.  */    X_REG_M, /* Only used for argument parsing.  */    DX_REG_N,    DX_REG_M,    V_REG_N,    V_REG_M,    XMTRX_M4,    F_FR0,    FPUL_N,    FPUL_M,    FPSCR_N,    FPSCR_M  }sh_arg_type;typedef enum  {    A_A1_NUM =   5,    A_A0_NUM =   7,    A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,    A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM  }sh_dsp_reg_nums;#define arch_sh1_base	0x0001#define arch_sh2_base	0x0002#define arch_sh3_base	0x0004#define arch_sh4_base	0x0008#define arch_sh4a_base	0x0010#define arch_sh2a_base  0x0020/* This is an annotation on instruction types, but we abuse the arch   field in instructions to denote it.  */#define arch_op32       0x00100000 /* This is a 32-bit opcode.  */#define arch_sh_no_mmu	0x04000000#define arch_sh_has_mmu 0x08000000#define arch_sh_no_co	0x10000000 /* neither FPU nor DSP co-processor */#define arch_sh_sp_fpu	0x20000000 /* single precision FPU */#define arch_sh_dp_fpu	0x40000000 /* double precision FPU */#define arch_sh_has_dsp	0x80000000#define arch_sh_base_mask 0x0000003f#define arch_opann_mask   0x00100000#define arch_sh_mmu_mask  0x0c000000#define arch_sh_co_mask   0xf0000000#define arch_sh1	(arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)#define arch_sh2	(arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)#define arch_sh2a	(arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)#define arch_sh2a_nofpu	(arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)#define arch_sh2e	(arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)#define arch_sh_dsp	(arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)#define arch_sh3_nommu	(arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)#define arch_sh3	(arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)#define arch_sh3e	(arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)#define arch_sh3_dsp	(arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)#define arch_sh4	(arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)#define arch_sh4a	(arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)#define arch_sh4al_dsp	(arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)#define arch_sh4_nofpu	(arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)#define arch_sh4a_nofpu	(arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)#define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)#define SH_VALID_MMU_ARCH_SET(SET)  (((SET) & arch_sh_mmu_mask) != 0)#define SH_VALID_CO_ARCH_SET(SET)   (((SET) & arch_sh_co_mask) != 0)#define SH_VALID_ARCH_SET(SET) \  (SH_VALID_BASE_ARCH_SET (SET) \   && SH_VALID_MMU_ARCH_SET (SET) \   && SH_VALID_CO_ARCH_SET (SET))