?? monitor.c
字號:
static target_long monitor_get_reg(struct MonitorDef *md, int val){ CPUState *env = mon_get_cpu(); if (!env) return 0; return env->regwptr[val];}#endifstatic MonitorDef monitor_defs[] = {#ifdef TARGET_I386#define SEG(name, seg) \ { name, offsetof(CPUState, segs[seg].selector), NULL, MD_I32 },\ { name ".base", offsetof(CPUState, segs[seg].base) },\ { name ".limit", offsetof(CPUState, segs[seg].limit), NULL, MD_I32 }, { "eax", offsetof(CPUState, regs[0]) }, { "ecx", offsetof(CPUState, regs[1]) }, { "edx", offsetof(CPUState, regs[2]) }, { "ebx", offsetof(CPUState, regs[3]) }, { "esp|sp", offsetof(CPUState, regs[4]) }, { "ebp|fp", offsetof(CPUState, regs[5]) }, { "esi", offsetof(CPUState, regs[6]) }, { "edi", offsetof(CPUState, regs[7]) },#ifdef TARGET_X86_64 { "r8", offsetof(CPUState, regs[8]) }, { "r9", offsetof(CPUState, regs[9]) }, { "r10", offsetof(CPUState, regs[10]) }, { "r11", offsetof(CPUState, regs[11]) }, { "r12", offsetof(CPUState, regs[12]) }, { "r13", offsetof(CPUState, regs[13]) }, { "r14", offsetof(CPUState, regs[14]) }, { "r15", offsetof(CPUState, regs[15]) },#endif { "eflags", offsetof(CPUState, eflags) }, { "eip", offsetof(CPUState, eip) }, SEG("cs", R_CS) SEG("ds", R_DS) SEG("es", R_ES) SEG("ss", R_SS) SEG("fs", R_FS) SEG("gs", R_GS) { "pc", 0, monitor_get_pc, },#elif defined(TARGET_PPC) /* General purpose registers */ { "r0", offsetof(CPUState, gpr[0]) }, { "r1", offsetof(CPUState, gpr[1]) }, { "r2", offsetof(CPUState, gpr[2]) }, { "r3", offsetof(CPUState, gpr[3]) }, { "r4", offsetof(CPUState, gpr[4]) }, { "r5", offsetof(CPUState, gpr[5]) }, { "r6", offsetof(CPUState, gpr[6]) }, { "r7", offsetof(CPUState, gpr[7]) }, { "r8", offsetof(CPUState, gpr[8]) }, { "r9", offsetof(CPUState, gpr[9]) }, { "r10", offsetof(CPUState, gpr[10]) }, { "r11", offsetof(CPUState, gpr[11]) }, { "r12", offsetof(CPUState, gpr[12]) }, { "r13", offsetof(CPUState, gpr[13]) }, { "r14", offsetof(CPUState, gpr[14]) }, { "r15", offsetof(CPUState, gpr[15]) }, { "r16", offsetof(CPUState, gpr[16]) }, { "r17", offsetof(CPUState, gpr[17]) }, { "r18", offsetof(CPUState, gpr[18]) }, { "r19", offsetof(CPUState, gpr[19]) }, { "r20", offsetof(CPUState, gpr[20]) }, { "r21", offsetof(CPUState, gpr[21]) }, { "r22", offsetof(CPUState, gpr[22]) }, { "r23", offsetof(CPUState, gpr[23]) }, { "r24", offsetof(CPUState, gpr[24]) }, { "r25", offsetof(CPUState, gpr[25]) }, { "r26", offsetof(CPUState, gpr[26]) }, { "r27", offsetof(CPUState, gpr[27]) }, { "r28", offsetof(CPUState, gpr[28]) }, { "r29", offsetof(CPUState, gpr[29]) }, { "r30", offsetof(CPUState, gpr[30]) }, { "r31", offsetof(CPUState, gpr[31]) }, /* Floating point registers */ { "f0", offsetof(CPUState, fpr[0]) }, { "f1", offsetof(CPUState, fpr[1]) }, { "f2", offsetof(CPUState, fpr[2]) }, { "f3", offsetof(CPUState, fpr[3]) }, { "f4", offsetof(CPUState, fpr[4]) }, { "f5", offsetof(CPUState, fpr[5]) }, { "f6", offsetof(CPUState, fpr[6]) }, { "f7", offsetof(CPUState, fpr[7]) }, { "f8", offsetof(CPUState, fpr[8]) }, { "f9", offsetof(CPUState, fpr[9]) }, { "f10", offsetof(CPUState, fpr[10]) }, { "f11", offsetof(CPUState, fpr[11]) }, { "f12", offsetof(CPUState, fpr[12]) }, { "f13", offsetof(CPUState, fpr[13]) }, { "f14", offsetof(CPUState, fpr[14]) }, { "f15", offsetof(CPUState, fpr[15]) }, { "f16", offsetof(CPUState, fpr[16]) }, { "f17", offsetof(CPUState, fpr[17]) }, { "f18", offsetof(CPUState, fpr[18]) }, { "f19", offsetof(CPUState, fpr[19]) }, { "f20", offsetof(CPUState, fpr[20]) }, { "f21", offsetof(CPUState, fpr[21]) }, { "f22", offsetof(CPUState, fpr[22]) }, { "f23", offsetof(CPUState, fpr[23]) }, { "f24", offsetof(CPUState, fpr[24]) }, { "f25", offsetof(CPUState, fpr[25]) }, { "f26", offsetof(CPUState, fpr[26]) }, { "f27", offsetof(CPUState, fpr[27]) }, { "f28", offsetof(CPUState, fpr[28]) }, { "f29", offsetof(CPUState, fpr[29]) }, { "f30", offsetof(CPUState, fpr[30]) }, { "f31", offsetof(CPUState, fpr[31]) }, { "fpscr", offsetof(CPUState, fpscr) }, /* Next instruction pointer */ { "nip|pc", offsetof(CPUState, nip) }, { "lr", offsetof(CPUState, lr) }, { "ctr", offsetof(CPUState, ctr) }, { "decr", 0, &monitor_get_decr, }, { "ccr", 0, &monitor_get_ccr, }, /* Machine state register */ { "msr", 0, &monitor_get_msr, }, { "xer", 0, &monitor_get_xer, }, { "tbu", 0, &monitor_get_tbu, }, { "tbl", 0, &monitor_get_tbl, },#if defined(TARGET_PPC64) /* Address space register */ { "asr", offsetof(CPUState, asr) },#endif /* Segment registers */ { "sdr1", offsetof(CPUState, sdr1) }, { "sr0", offsetof(CPUState, sr[0]) }, { "sr1", offsetof(CPUState, sr[1]) }, { "sr2", offsetof(CPUState, sr[2]) }, { "sr3", offsetof(CPUState, sr[3]) }, { "sr4", offsetof(CPUState, sr[4]) }, { "sr5", offsetof(CPUState, sr[5]) }, { "sr6", offsetof(CPUState, sr[6]) }, { "sr7", offsetof(CPUState, sr[7]) }, { "sr8", offsetof(CPUState, sr[8]) }, { "sr9", offsetof(CPUState, sr[9]) }, { "sr10", offsetof(CPUState, sr[10]) }, { "sr11", offsetof(CPUState, sr[11]) }, { "sr12", offsetof(CPUState, sr[12]) }, { "sr13", offsetof(CPUState, sr[13]) }, { "sr14", offsetof(CPUState, sr[14]) }, { "sr15", offsetof(CPUState, sr[15]) }, /* Too lazy to put BATs and SPRs ... */#elif defined(TARGET_SPARC) { "g0", offsetof(CPUState, gregs[0]) }, { "g1", offsetof(CPUState, gregs[1]) }, { "g2", offsetof(CPUState, gregs[2]) }, { "g3", offsetof(CPUState, gregs[3]) }, { "g4", offsetof(CPUState, gregs[4]) }, { "g5", offsetof(CPUState, gregs[5]) }, { "g6", offsetof(CPUState, gregs[6]) }, { "g7", offsetof(CPUState, gregs[7]) }, { "o0", 0, monitor_get_reg }, { "o1", 1, monitor_get_reg }, { "o2", 2, monitor_get_reg }, { "o3", 3, monitor_get_reg }, { "o4", 4, monitor_get_reg }, { "o5", 5, monitor_get_reg }, { "o6", 6, monitor_get_reg }, { "o7", 7, monitor_get_reg }, { "l0", 8, monitor_get_reg }, { "l1", 9, monitor_get_reg }, { "l2", 10, monitor_get_reg }, { "l3", 11, monitor_get_reg }, { "l4", 12, monitor_get_reg }, { "l5", 13, monitor_get_reg }, { "l6", 14, monitor_get_reg }, { "l7", 15, monitor_get_reg }, { "i0", 16, monitor_get_reg }, { "i1", 17, monitor_get_reg }, { "i2", 18, monitor_get_reg }, { "i3", 19, monitor_get_reg }, { "i4", 20, monitor_get_reg }, { "i5", 21, monitor_get_reg }, { "i6", 22, monitor_get_reg }, { "i7", 23, monitor_get_reg }, { "pc", offsetof(CPUState, pc) }, { "npc", offsetof(CPUState, npc) }, { "y", offsetof(CPUState, y) },#ifndef TARGET_SPARC64 { "psr", 0, &monitor_get_psr, }, { "wim", offsetof(CPUState, wim) },#endif { "tbr", offsetof(CPUState, tbr) }, { "fsr", offsetof(CPUState, fsr) }, { "f0", offsetof(CPUState, fpr[0]) }, { "f1", offsetof(CPUState, fpr[1]) }, { "f2", offsetof(CPUState, fpr[2]) }, { "f3", offsetof(CPUState, fpr[3]) }, { "f4", offsetof(CPUState, fpr[4]) }, { "f5", offsetof(CPUState, fpr[5]) }, { "f6", offsetof(CPUState, fpr[6]) }, { "f7", offsetof(CPUState, fpr[7]) }, { "f8", offsetof(CPUState, fpr[8]) }, { "f9", offsetof(CPUState, fpr[9]) }, { "f10", offsetof(CPUState, fpr[10]) }, { "f11", offsetof(CPUState, fpr[11]) }, { "f12", offsetof(CPUState, fpr[12]) }, { "f13", offsetof(CPUState, fpr[13]) }, { "f14", offsetof(CPUState, fpr[14]) }, { "f15", offsetof(CPUState, fpr[15]) }, { "f16", offsetof(CPUState, fpr[16]) }, { "f17", offsetof(CPUState, fpr[17]) }, { "f18", offsetof(CPUState, fpr[18]) }, { "f19", offsetof(CPUState, fpr[19]) }, { "f20", offsetof(CPUState, fpr[20]) }, { "f21", offsetof(CPUState, fpr[21]) }, { "f22", offsetof(CPUState, fpr[22]) }, { "f23", offsetof(CPUState, fpr[23]) }, { "f24", offsetof(CPUState, fpr[24]) }, { "f25", offsetof(CPUState, fpr[25]) }, { "f26", offsetof(CPUState, fpr[26]) }, { "f27", offsetof(CPUState, fpr[27]) }, { "f28", offsetof(CPUState, fpr[28]) }, { "f29", offsetof(CPUState, fpr[29]) }, { "f30", offsetof(CPUState, fpr[30]) }, { "f31", offsetof(CPUState, fpr[31]) },#ifdef TARGET_SPARC64 { "f32", offsetof(CPUState, fpr[32]) }, { "f34", offsetof(CPUState, fpr[34]) }, { "f36", offsetof(CPUState, fpr[36]) }, { "f38", offsetof(CPUState, fpr[38]) }, { "f40", offsetof(CPUState, fpr[40]) }, { "f42", offsetof(CPUState, fpr[42]) }, { "f44", offsetof(CPUState, fpr[44]) }, { "f46", offsetof(CPUState, fpr[46]) }, { "f48", offsetof(CPUState, fpr[48]) }, { "f50", offsetof(CPUState, fpr[50]) }, { "f52", offsetof(CPUState, fpr[52]) }, { "f54", offsetof(CPUState, fpr[54]) }, { "f56", offsetof(CPUState, fpr[56]) }, { "f58", offsetof(CPUState, fpr[58]) }, { "f60", offsetof(CPUState, fpr[60]) }, { "f62", offsetof(CPUState, fpr[62]) }, { "asi", offsetof(CPUState, asi) }, { "pstate", offsetof(CPUState, pstate) }, { "cansave", offsetof(CPUState, cansave) }, { "canrestore", offsetof(CPUState, canrestore) }, { "otherwin", offsetof(CPUState, otherwin) }, { "wstate", offsetof(CPUState, wstate) }, { "cleanwin", offsetof(CPUState, cleanwin) }, { "fprs", offsetof(CPUState, fprs) },#endif#endif { NULL },};static void expr_error(const char *fmt){ term_printf(fmt); term_printf("\n"); longjmp(expr_env, 1);}/* return 0 if OK, -1 if not found, -2 if no CPU defined */static int get_monitor_def(target_long *pval, const char *name){ MonitorDef *md; void *ptr; for(md = monitor_defs; md->name != NULL; md++) { if (compare_cmd(name, md->name)) { if (md->get_value) { *pval = md->get_value(md, md->offset); } else { CPUState *env = mon_get_cpu(); if (!env) return -2; ptr = (uint8_t *)env + md->offset; switch(md->type) { case MD_I32: *pval = *(int32_t *)ptr; break; case MD_TLONG: *pval = *(target_long *)ptr; break; default: *pval = 0; break; } } return 0; } } return -1;}static void next(void){ if (pch != '\0') { pch++; while (isspace(*pch)) pch++; }}static int64_t expr_sum(void);static int64_t expr_unary(void){ int64_t n; char *p; int ret; switch(*pch) { case '+': next(); n = expr_unary(); break; case '-': next(); n = -expr_unary(); break; case '~': next(); n = ~expr_unary(); break; case '(': next(); n = expr_sum(); if (*pch != ')') { expr_error("')' expected"); } next(); break; case '\'': pch++; if (*pch == '\0') expr_error("character constant expected"); n = *pch; pch++; if (*pch != '\'') expr_error("missing terminating \' character"); next(); break; case '$': { char buf[128], *q; target_long reg=0; pch++; q = buf; while ((*pch >= 'a' && *pch <= 'z') || (*pch >= 'A' && *pch <= 'Z') || (*pch >= '0' && *pch <= '9') || *pch == '_' || *pch == '.') { if ((q - buf) < sizeof(buf) - 1) *q++ = *pch; pch++; } while (isspace(*pch)) pch++; *q = 0; ret = get_monitor_def(®, buf); if (ret == -1) expr_error("unknown register"); else if (ret == -2) expr_error("no cpu defined"); n = reg; } break; case '\0': expr_error("unexpected end of expression"); n = 0; break; default:#if TARGET_PHYS_ADDR_BITS > 32 n = strtoull(pch, &p, 0);#else n = strtoul(pch, &p, 0);#endif if (pch == p) { expr_error("invalid char in expression"); } pch = p; while (isspace(*pch)) pch++; break; } return n;}static int64_t expr_prod(void){ int64_t val, val2; int op; val = expr_unary(); for(;;) { op = *pch; if (op != '*' && op != '/' && op != '%') break; next(); val2 = expr_unary(); switch(op) { default: case '*': val *= val2; break; case '/': case '%': if (val2 == 0) expr_error("division by zero"); if (op == '/') val /= val2; else val %= val2; break; } } return val;}static int64_t expr_logic(void){ int64_t val, val2; int op; val = expr_prod(); for(;;) { op = *pch; if (op != '&' && op != '|' && op != '^') break; next(); val2 = expr_prod(); switch(op) { default: case '&': val &= val2; break; case '|': val |= val2; break; case '^': val ^= val2; break; } } return val;}static int64_t expr_sum(void){ int64_t val, val2; int op; val = expr_logic(); for(;;) { op = *pch; if (op != '+' && op != '-') break; next(); val2 = expr_logic(); if (op == '+') val += val2; else val -= val2; } return val;}static int get_expr(int64_t *pval, const char **pp){ pch = *pp; if (setjmp(expr_env)) { *pp = pch; return -1; } while (isspace(*pch)) pch++; *pval = expr_sum(); *pp = pch; return 0;}static int get_str(char *buf, int buf_size, const char **pp){ const char *p; char *q; int c; q = buf; p = *pp; while (isspace(*p)) p++; if (*p == '\0') { fail: *q = '\0'; *pp = p; return -1; }?? 快捷鍵說明
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