#define F3(x, y, z)     (OP(x) | OP3(y) | F3I(z)) /* format3 insns */#define F1(x)           (OP(x))#define DISP30(x)       ((x)&0x3fffffff)#define ASI(x)          (((x)&0xff) << 5) /* asi field of format3 insns */#define RS2(x)          ((x)&0x1f) /* rs2 field */#define SIMM13(x)       ((x)&0x1fff) /* simm13 field */#define RD(x)           (((x)&0x1f) << 25) /* destination register field */#define RS1(x)          (((x)&0x1f) << 14) /* rs1 field */#define ASI_RS2(x)      (SIMM13(x))#define MEMBAR(x)       ((x)&0x7f)#define SLCPOP(x)       (((x)&0x7f) << 6) /* sparclet cpop */#define ANNUL   (1<<29)#define BPRED   (1<<19) /* v9 */#define IMMED   F3I(1)#define RD_G0   RD(~0)#define RS1_G0  RS1(~0)#define RS2_G0  RS2(~0)extern const struct sparc_opcode sparc_opcodes[];extern const int sparc_num_opcodes;extern int sparc_encode_asi PARAMS ((const char *));extern const char *sparc_decode_asi PARAMS ((int));extern int sparc_encode_membar PARAMS ((const char *));extern const char *sparc_decode_membar PARAMS ((int));extern int sparc_encode_prefetch PARAMS ((const char *));extern const char *sparc_decode_prefetch PARAMS ((int));extern int sparc_encode_sparclet_cpreg PARAMS ((const char *));extern const char *sparc_decode_sparclet_cpreg PARAMS ((int));/* Some defines to make life easy.  */#define MASK_V6         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)#define MASK_V7         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)#define MASK_V8         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)#define MASK_SPARCLET   SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)#define MASK_SPARCLITE  SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)#define MASK_V9         SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)#define MASK_V9A        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)#define MASK_V9B        SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)/* Bit masks of architectures supporting the insn.  */#define v6              (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)/* v6 insns not supported on the sparclet */#define v6notlet        (MASK_V6 | MASK_V7 | MASK_V8 \                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)#define v7              (MASK_V7 | MASK_V8 | MASK_SPARCLET \                         | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)/* Although not all insns are implemented in hardware, sparclite is defined   to be a superset of v8.  Unimplemented insns trap and are then theoretically   implemented in software.   It's not clear that the same is true for sparclet, although the docs   suggest it is.  Rather than complicating things, the sparclet assembler   recognizes all v8 insns.  */#define v8              (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \                         | MASK_V9 | MASK_V9A | MASK_V9B)#define sparclet        (MASK_SPARCLET)#define sparclite       (MASK_SPARCLITE)#define v9              (MASK_V9 | MASK_V9A | MASK_V9B)#define v9a             (MASK_V9A | MASK_V9B)#define v9b             (MASK_V9B)/* v6 insns not supported by v9 */#define v6notv9         (MASK_V6 | MASK_V7 | MASK_V8 \                         | MASK_SPARCLET | MASK_SPARCLITE)/* v9a instructions which would appear to be aliases to v9's impdep's   otherwise */#define v9notv9a        (MASK_V9)/* Table of opcode architectures.   The order is defined in opcode/sparc.h.  */const struct sparc_opcode_arch sparc_opcode_archs[] = {  { "v6", MASK_V6 },  { "v7", MASK_V6 | MASK_V7 },  { "v8", MASK_V6 | MASK_V7 | MASK_V8 },  { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },  { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },  /* ??? Don't some v8 privileged insns conflict with v9?  */  { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },  /* v9 with ultrasparc additions */  { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },  /* v9 with cheetah additions */  { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },  { NULL, 0 }};/* Given NAME, return it's architecture entry.  */enum sparc_opcode_arch_valsparc_opcode_lookup_arch (name)     const char *name;{  const struct sparc_opcode_arch *p;  for (p = &sparc_opcode_archs[0]; p->name; ++p)    {      if (strcmp (name, p->name) == 0)        return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);    }  return SPARC_OPCODE_ARCH_BAD;}/* Branch condition field.  */#define COND(x)         (((x)&0xf)<<25)/* v9: Move (MOVcc and FMOVcc) condition field.  */#define MCOND(x,i_or_f) ((((i_or_f)&1)<<18)|(((x)>>11)&(0xf<<14))) /* v9 *//* v9: Move register (MOVRcc and FMOVRcc) condition field.  */#define RCOND(x)        (((x)&0x7)<<10) /* v9 */#define CONDA   (COND(0x8))#define CONDCC  (COND(0xd))#define CONDCS  (COND(0x5))#define CONDE   (COND(0x1))#define CONDG   (COND(0xa))#define CONDGE  (COND(0xb))#define CONDGU  (COND(0xc))#define CONDL   (COND(0x3))#define CONDLE  (COND(0x2))#define CONDLEU (COND(0x4))#define CONDN   (COND(0x0))#define CONDNE  (COND(0x9))#define CONDNEG (COND(0x6))#define CONDPOS (COND(0xe))#define CONDVC  (COND(0xf))#define CONDVS  (COND(0x7))#define CONDNZ  CONDNE#define CONDZ   CONDE#define CONDGEU CONDCC#define CONDLU  CONDCS#define FCONDA          (COND(0x8))#define FCONDE          (COND(0x9))#define FCONDG          (COND(0x6))#define FCONDGE         (COND(0xb))#define FCONDL          (COND(0x4))#define FCONDLE         (COND(0xd))#define FCONDLG         (COND(0x2))#define FCONDN          (COND(0x0))#define FCONDNE         (COND(0x1))#define FCONDO          (COND(0xf))#define FCONDU          (COND(0x7))#define FCONDUE         (COND(0xa))#define FCONDUG         (COND(0x5))#define FCONDUGE        (COND(0xc))#define FCONDUL         (COND(0x3))#define FCONDULE        (COND(0xe))#define FCONDNZ FCONDNE#define FCONDZ  FCONDE#define ICC (0) /* v9 */#define XCC (1<<12) /* v9 */#define FCC(x)  (((x)&0x3)<<11) /* v9 */#define FBFCC(x)        (((x)&0x3)<<20) /* v9 *//* The order of the opcodes in the table is significant:        * The assembler requires that all instances of the same mnemonic must        be consecutive. If they aren't, the assembler will bomb at runtime.        * The disassembler should not care about the order of the opcodes.*//* Entries for commutative arithmetic operations.  *//* ??? More entries can make use of this.  */#define COMMUTEOP(opcode, op3, arch_mask) \{ opcode,       F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),        "1,2,d", 0, arch_mask }, \{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "1,i,d", 0, arch_mask }, \{ opcode,       F3(2, op3, 1), F3(~2, ~op3, ~1),                "i,1,d", 0, arch_mask }const struct sparc_opcode sparc_opcodes[] = {{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0),              "[1+2],d", 0, v6 },{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,       "[1],d", 0, v6 }, /* ld [rs1+%g0],d */{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[1+i],d", 0, v6 },{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1),              "[i+1],d", 0, v6 },{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,       "[i],d", 0, v6 },{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),   "[1],d", 0, v6 }, /* ld [rs1+0],d */{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0),              "[1+2],g", 0, v6 },{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,       "[1],g", 0, v6 }, /* ld [rs1+%g0],d */{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[1+i],g", 0, v6 },{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1),              "[i+1],g", 0, v6 },{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,       "[i],g", 0, v6 },{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),   "[1],g", 0, v6 }, /* ld [rs1+0],d */{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),       "[1+2],F", 0, v6 },{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[1+i],F", 0, v6 },{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),       "[i+1],F", 0, v6 },{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */