#define CPU_MIPS16	16#define CPU_MIPS32	32#define CPU_MIPS32R2	33#define CPU_MIPS5       5#define CPU_MIPS64      64#define CPU_MIPS64R2	65#define CPU_SB1         12310201        /* octal 'SB', 01.  *//* Test for membership in an ISA including chip specific ISAs.  INSN   is pointer to an element of the opcode table; ISA is the specified   ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to   test, or zero if no CPU specific ISA test is desired.  */#if 0#define OPCODE_IS_MEMBER(insn, isa, cpu)				\    (((insn)->membership & isa) != 0					\     || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)	\     || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)	\     || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)	\     || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)	\     || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)	\     || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)	\     || ((cpu == CPU_R10000 || cpu == CPU_R12000)			\	 && ((insn)->membership & INSN_10000) != 0)			\     || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)	\     || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)	\     || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)	\     || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)	\     || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)	\     || 0)	/* Please keep this term for easier source merging.  */#else#define OPCODE_IS_MEMBER(insn, isa, cpu)                               \    (1 != 0)#endif/* This is a list of macro expanded instructions.   _I appended means immediate   _A appended means address   _AB appended means address with base register   _D appended means 64 bit floating point constant   _S appended means 32 bit floating point constant.  */enum{  M_ABS,  M_ADD_I,  M_ADDU_I,  M_AND_I,  M_BALIGN,  M_BEQ,  M_BEQ_I,  M_BEQL_I,  M_BGE,  M_BGEL,  M_BGE_I,  M_BGEL_I,  M_BGEU,  M_BGEUL,  M_BGEU_I,  M_BGEUL_I,  M_BGT,  M_BGTL,  M_BGT_I,  M_BGTL_I,  M_BGTU,  M_BGTUL,  M_BGTU_I,  M_BGTUL_I,  M_BLE,  M_BLEL,  M_BLE_I,  M_BLEL_I,  M_BLEU,  M_BLEUL,  M_BLEU_I,  M_BLEUL_I,  M_BLT,  M_BLTL,  M_BLT_I,  M_BLTL_I,  M_BLTU,  M_BLTUL,  M_BLTU_I,  M_BLTUL_I,  M_BNE,  M_BNE_I,  M_BNEL_I,  M_CACHE_AB,  M_DABS,  M_DADD_I,  M_DADDU_I,  M_DDIV_3,  M_DDIV_3I,  M_DDIVU_3,  M_DDIVU_3I,  M_DEXT,  M_DINS,  M_DIV_3,  M_DIV_3I,  M_DIVU_3,  M_DIVU_3I,  M_DLA_AB,  M_DLCA_AB,  M_DLI,  M_DMUL,  M_DMUL_I,  M_DMULO,  M_DMULO_I,  M_DMULOU,  M_DMULOU_I,  M_DREM_3,  M_DREM_3I,  M_DREMU_3,  M_DREMU_3I,  M_DSUB_I,  M_DSUBU_I,  M_DSUBU_I_2,  M_J_A,  M_JAL_1,  M_JAL_2,  M_JAL_A,  M_L_DOB,  M_L_DAB,  M_LA_AB,  M_LB_A,  M_LB_AB,  M_LBU_A,  M_LBU_AB,  M_LCA_AB,  M_LD_A,  M_LD_OB,  M_LD_AB,  M_LDC1_AB,  M_LDC2_AB,  M_LDC3_AB,  M_LDL_AB,  M_LDR_AB,  M_LH_A,  M_LH_AB,  M_LHU_A,  M_LHU_AB,  M_LI,  M_LI_D,  M_LI_DD,  M_LI_S,  M_LI_SS,  M_LL_AB,  M_LLD_AB,  M_LS_A,  M_LW_A,  M_LW_AB,  M_LWC0_A,  M_LWC0_AB,  M_LWC1_A,  M_LWC1_AB,  M_LWC2_A,  M_LWC2_AB,  M_LWC3_A,  M_LWC3_AB,  M_LWL_A,  M_LWL_AB,  M_LWR_A,  M_LWR_AB,  M_LWU_AB,  M_MOVE,  M_MUL,  M_MUL_I,  M_MULO,  M_MULO_I,  M_MULOU,  M_MULOU_I,  M_NOR_I,  M_OR_I,  M_REM_3,  M_REM_3I,  M_REMU_3,  M_REMU_3I,  M_DROL,  M_ROL,  M_DROL_I,  M_ROL_I,  M_DROR,  M_ROR,  M_DROR_I,  M_ROR_I,  M_S_DA,  M_S_DOB,  M_S_DAB,  M_S_S,  M_SC_AB,  M_SCD_AB,  M_SD_A,  M_SD_OB,  M_SD_AB,  M_SDC1_AB,  M_SDC2_AB,  M_SDC3_AB,  M_SDL_AB,  M_SDR_AB,  M_SEQ,  M_SEQ_I,  M_SGE,  M_SGE_I,  M_SGEU,  M_SGEU_I,  M_SGT,  M_SGT_I,  M_SGTU,  M_SGTU_I,  M_SLE,  M_SLE_I,  M_SLEU,  M_SLEU_I,  M_SLT_I,  M_SLTU_I,  M_SNE,  M_SNE_I,  M_SB_A,  M_SB_AB,  M_SH_A,  M_SH_AB,  M_SW_A,  M_SW_AB,  M_SWC0_A,  M_SWC0_AB,  M_SWC1_A,  M_SWC1_AB,  M_SWC2_A,  M_SWC2_AB,  M_SWC3_A,  M_SWC3_AB,  M_SWL_A,  M_SWL_AB,  M_SWR_A,  M_SWR_AB,  M_SUB_I,  M_SUBU_I,  M_SUBU_I_2,  M_TEQ_I,  M_TGE_I,  M_TGEU_I,  M_TLT_I,  M_TLTU_I,  M_TNE_I,  M_TRUNCWD,  M_TRUNCWS,  M_ULD,  M_ULD_A,  M_ULH,  M_ULH_A,  M_ULHU,  M_ULHU_A,  M_ULW,  M_ULW_A,  M_USH,  M_USH_A,  M_USW,  M_USW_A,  M_USD,  M_USD_A,  M_XOR_I,  M_COP0,  M_COP1,  M_COP2,  M_COP3,  M_NUM_MACROS};/* The order of overloaded instructions matters.  Label arguments and   register arguments look the same. Instructions that can have either   for arguments must apear in the correct order in this table for the   assembler to pick the right one. In other words, entries with   immediate operands must apear after the same instruction with   registers.   Many instructions are short hand for other instructions (i.e., The   jal <register> instruction is short for jalr <register>).  */extern const struct mips_opcode mips_builtin_opcodes[];extern const int bfd_mips_num_builtin_opcodes;extern struct mips_opcode *mips_opcodes;extern int bfd_mips_num_opcodes;#define NUMOPCODES bfd_mips_num_opcodes/* The rest of this file adds definitions for the mips16 TinyRISC   processor.  *//* These are the bitmasks and shift counts used for the different   fields in the instruction formats.  Other than OP, no masks are   provided for the fixed portions of an instruction, since they are   not needed.   The I format uses IMM11.   The RI format uses RX and IMM8.   The RR format uses RX, and RY.   The RRI format uses RX, RY, and IMM5.   The RRR format uses RX, RY, and RZ.   The RRI_A format uses RX, RY, and IMM4.   The SHIFT format uses RX, RY, and SHAMT.   The I8 format uses IMM8.   The I8_MOVR32 format uses RY and REGR32.   The IR_MOV32R format uses REG32R and MOV32Z.