case 0x314: case 0x714: case 0xb14: case 0xf14:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        switch ((insn >> 22) & 3) {        case 0:            return 1;        case 1:            if (gen_iwmmxt_shift(insn, 0xf))                return 1;            gen_op_iwmmxt_rorw_M0_T0();            break;        case 2:            if (gen_iwmmxt_shift(insn, 0x1f))                return 1;            gen_op_iwmmxt_rorl_M0_T0();            break;        case 3:            if (gen_iwmmxt_shift(insn, 0x3f))                return 1;            gen_op_iwmmxt_rorq_M0_T0();            break;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        gen_op_iwmmxt_set_cup();        break;    case 0x116: case 0x316: case 0x516: case 0x716:	/* WMIN */    case 0x916: case 0xb16: case 0xd16: case 0xf16:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        switch ((insn >> 22) & 3) {        case 0:            if (insn & (1 << 21))                gen_op_iwmmxt_minsb_M0_wRn(rd1);            else                gen_op_iwmmxt_minub_M0_wRn(rd1);            break;        case 1:            if (insn & (1 << 21))                gen_op_iwmmxt_minsw_M0_wRn(rd1);            else                gen_op_iwmmxt_minuw_M0_wRn(rd1);            break;        case 2:            if (insn & (1 << 21))                gen_op_iwmmxt_minsl_M0_wRn(rd1);            else                gen_op_iwmmxt_minul_M0_wRn(rd1);            break;        case 3:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        break;    case 0x016: case 0x216: case 0x416: case 0x616:	/* WMAX */    case 0x816: case 0xa16: case 0xc16: case 0xe16:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        switch ((insn >> 22) & 3) {        case 0:            if (insn & (1 << 21))                gen_op_iwmmxt_maxsb_M0_wRn(rd1);            else                gen_op_iwmmxt_maxub_M0_wRn(rd1);            break;        case 1:            if (insn & (1 << 21))                gen_op_iwmmxt_maxsw_M0_wRn(rd1);            else                gen_op_iwmmxt_maxuw_M0_wRn(rd1);            break;        case 2:            if (insn & (1 << 21))                gen_op_iwmmxt_maxsl_M0_wRn(rd1);            else                gen_op_iwmmxt_maxul_M0_wRn(rd1);            break;        case 3:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        break;    case 0x002: case 0x102: case 0x202: case 0x302:	/* WALIGNI */    case 0x402: case 0x502: case 0x602: case 0x702:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        gen_op_movl_T0_im((insn >> 20) & 3);        gen_op_iwmmxt_align_M0_T0_wRn(rd1);        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        break;    case 0x01a: case 0x11a: case 0x21a: case 0x31a:	/* WSUB */    case 0x41a: case 0x51a: case 0x61a: case 0x71a:    case 0x81a: case 0x91a: case 0xa1a: case 0xb1a:    case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        switch ((insn >> 20) & 0xf) {        case 0x0:            gen_op_iwmmxt_subnb_M0_wRn(rd1);            break;        case 0x1:            gen_op_iwmmxt_subub_M0_wRn(rd1);            break;        case 0x3:            gen_op_iwmmxt_subsb_M0_wRn(rd1);            break;        case 0x4:            gen_op_iwmmxt_subnw_M0_wRn(rd1);            break;        case 0x5:            gen_op_iwmmxt_subuw_M0_wRn(rd1);            break;        case 0x7:            gen_op_iwmmxt_subsw_M0_wRn(rd1);            break;        case 0x8:            gen_op_iwmmxt_subnl_M0_wRn(rd1);            break;        case 0x9:            gen_op_iwmmxt_subul_M0_wRn(rd1);            break;        case 0xb:            gen_op_iwmmxt_subsl_M0_wRn(rd1);            break;        default:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        gen_op_iwmmxt_set_cup();        break;    case 0x01e: case 0x11e: case 0x21e: case 0x31e:	/* WSHUFH */    case 0x41e: case 0x51e: case 0x61e: case 0x71e:    case 0x81e: case 0x91e: case 0xa1e: case 0xb1e:    case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        gen_op_movl_T0_im(((insn >> 16) & 0xf0) | (insn & 0x0f));        gen_op_iwmmxt_shufh_M0_T0();        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        gen_op_iwmmxt_set_cup();        break;    case 0x018: case 0x118: case 0x218: case 0x318:	/* WADD */    case 0x418: case 0x518: case 0x618: case 0x718:    case 0x818: case 0x918: case 0xa18: case 0xb18:    case 0xc18: case 0xd18: case 0xe18: case 0xf18:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        switch ((insn >> 20) & 0xf) {        case 0x0:            gen_op_iwmmxt_addnb_M0_wRn(rd1);            break;        case 0x1:            gen_op_iwmmxt_addub_M0_wRn(rd1);            break;        case 0x3:            gen_op_iwmmxt_addsb_M0_wRn(rd1);            break;        case 0x4:            gen_op_iwmmxt_addnw_M0_wRn(rd1);            break;        case 0x5:            gen_op_iwmmxt_adduw_M0_wRn(rd1);            break;        case 0x7:            gen_op_iwmmxt_addsw_M0_wRn(rd1);            break;        case 0x8:            gen_op_iwmmxt_addnl_M0_wRn(rd1);            break;        case 0x9:            gen_op_iwmmxt_addul_M0_wRn(rd1);            break;        case 0xb:            gen_op_iwmmxt_addsl_M0_wRn(rd1);            break;        default:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        gen_op_iwmmxt_set_cup();        break;    case 0x008: case 0x108: case 0x208: case 0x308:	/* WPACK */    case 0x408: case 0x508: case 0x608: case 0x708:    case 0x808: case 0x908: case 0xa08: case 0xb08:    case 0xc08: case 0xd08: case 0xe08: case 0xf08:        wrd = (insn >> 12) & 0xf;        rd0 = (insn >> 16) & 0xf;        rd1 = (insn >> 0) & 0xf;        gen_op_iwmmxt_movq_M0_wRn(rd0);        if (!(insn & (1 << 20)))            return 1;        switch ((insn >> 22) & 3) {        case 0:            return 1;        case 1:            if (insn & (1 << 21))                gen_op_iwmmxt_packsw_M0_wRn(rd1);            else                gen_op_iwmmxt_packuw_M0_wRn(rd1);            break;        case 2:            if (insn & (1 << 21))                gen_op_iwmmxt_packsl_M0_wRn(rd1);            else                gen_op_iwmmxt_packul_M0_wRn(rd1);            break;        case 3:            if (insn & (1 << 21))                gen_op_iwmmxt_packsq_M0_wRn(rd1);            else                gen_op_iwmmxt_packuq_M0_wRn(rd1);            break;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        gen_op_iwmmxt_set_cup();        break;    case 0x201: case 0x203: case 0x205: case 0x207:    case 0x209: case 0x20b: case 0x20d: case 0x20f:    case 0x211: case 0x213: case 0x215: case 0x217:    case 0x219: case 0x21b: case 0x21d: case 0x21f:        wrd = (insn >> 5) & 0xf;        rd0 = (insn >> 12) & 0xf;        rd1 = (insn >> 0) & 0xf;        if (rd0 == 0xf || rd1 == 0xf)            return 1;        gen_op_iwmmxt_movq_M0_wRn(wrd);        switch ((insn >> 16) & 0xf) {        case 0x0:					/* TMIA */            gen_op_movl_TN_reg[0][rd0]();            gen_op_movl_TN_reg[1][rd1]();            gen_op_iwmmxt_muladdsl_M0_T0_T1();            break;        case 0x8:					/* TMIAPH */            gen_op_movl_TN_reg[0][rd0]();            gen_op_movl_TN_reg[1][rd1]();            gen_op_iwmmxt_muladdsw_M0_T0_T1();            break;        case 0xc: case 0xd: case 0xe: case 0xf:		/* TMIAxy */            gen_op_movl_TN_reg[1][rd0]();            if (insn & (1 << 16))                gen_op_shrl_T1_im(16);            gen_op_movl_T0_T1();            gen_op_movl_TN_reg[1][rd1]();            if (insn & (1 << 17))                gen_op_shrl_T1_im(16);            gen_op_iwmmxt_muladdswl_M0_T0_T1();            break;        default:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(wrd);        gen_op_iwmmxt_set_mup();        break;    default:        return 1;    }    return 0;}/* Disassemble an XScale DSP instruction.  Returns nonzero if an error occured   (ie. an undefined instruction).  */static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn){    int acc, rd0, rd1, rdhi, rdlo;    if ((insn & 0x0ff00f10) == 0x0e200010) {        /* Multiply with Internal Accumulate Format */        rd0 = (insn >> 12) & 0xf;        rd1 = insn & 0xf;        acc = (insn >> 5) & 7;        if (acc != 0)            return 1;        switch ((insn >> 16) & 0xf) {        case 0x0:					/* MIA */            gen_op_movl_TN_reg[0][rd0]();            gen_op_movl_TN_reg[1][rd1]();            gen_op_iwmmxt_muladdsl_M0_T0_T1();            break;        case 0x8:					/* MIAPH */            gen_op_movl_TN_reg[0][rd0]();            gen_op_movl_TN_reg[1][rd1]();            gen_op_iwmmxt_muladdsw_M0_T0_T1();            break;        case 0xc:					/* MIABB */        case 0xd:					/* MIABT */        case 0xe:					/* MIATB */        case 0xf:					/* MIATT */            gen_op_movl_TN_reg[1][rd0]();            if (insn & (1 << 16))                gen_op_shrl_T1_im(16);            gen_op_movl_T0_T1();            gen_op_movl_TN_reg[1][rd1]();            if (insn & (1 << 17))                gen_op_shrl_T1_im(16);            gen_op_iwmmxt_muladdswl_M0_T0_T1();            break;        default:            return 1;        }        gen_op_iwmmxt_movq_wRn_M0(acc);        return 0;    }    if ((insn & 0x0fe00ff8) == 0x0c400000) {        /* Internal Accumulator Access Format */        rdhi = (insn >> 16) & 0xf;        rdlo = (insn >> 12) & 0xf;        acc = insn & 7;        if (acc != 0)            return 1;        if (insn & ARM_CP_RW_BIT) {			/* MRA */            gen_op_iwmmxt_movl_T0_T1_wRn(acc);            gen_op_movl_reg_TN[0][rdlo]();            gen_op_movl_T0_im((1 << (40 - 32)) - 1);            gen_op_andl_T0_T1();            gen_op_movl_reg_TN[0][rdhi]();        } else {					/* MAR */            gen_op_movl_TN_reg[0][rdlo]();            gen_op_movl_TN_reg[1][rdhi]();            gen_op_iwmmxt_movl_wRn_T0_T1(acc);        }        return 0;    }    return 1;}/* Disassemble system coprocessor instruction.  Return nonzero if   instruction is not defined.  */static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn){    uint32_t rd = (insn >> 12) & 0xf;    uint32_t cp = (insn >> 8) & 0xf;    if (IS_USER(s)) {        return 1;    }    if (insn & ARM_CP_RW_BIT) {        if (!env->cp[cp].cp_read)            return 1;        gen_op_movl_T0_im((uint32_t) s->pc);        gen_op_movl_reg_TN[0][15]();        gen_op_movl_T0_cp(insn);        gen_movl_reg_T0(s, rd);    } else {        if (!env->cp[cp].cp_write)            return 1;        gen_op_movl_T0_im((uint32_t) s->pc);        gen_op_movl_reg_TN[0][15]();        gen_movl_T0_reg(s, rd);        gen_op_movl_cp_T0(insn);    }    return 0;}static int cp15_user_ok(uint32_t insn){    int cpn = (insn >> 16) & 0xf;    int cpm = insn & 0xf;    int op = ((insn >> 5) & 7) | ((insn >> 18) & 0x38);    if (cpn == 13 && cpm == 0) {        /* TLS register.  */        if (op == 2 || (op == 3 && (insn & ARM_CP_RW_BIT)))            return 1;    }    if (cpn == 7) {        /* ISB, DSB, DMB.  */        if ((cpm == 5 && op == 4)                || (cpm == 10 && (op == 4 || op == 5)))            return 1;    }    return 0;}/* Disassemble system coprocessor (cp15) instruction.  Return nonzero if   instruction is not defined.  */static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn){    uint32_t rd;    /* M profile cores use memory mapped registers instead of cp15.  */    if (arm_feature(env, ARM_FEATURE_M))	return 1;    if ((insn & (1 << 25)) == 0) {        if (insn & (1 << 20)) {            /* mrrc */            return 1;        }        /* mcrr.  Used for block cache operations, so implement as no-op.  */        return 0;    }    if ((insn & (1 << 4)) == 0) {        /* cdp */        return 1;    }    if (IS_USER(s) && !cp15_user_ok(insn)) {        return 1;    }    if ((insn & 0x0fff0fff) == 0x0e070f90        || (insn & 0x0fff0fff) == 0x0e070f58) {        /* Wait for interrupt.  */        gen_op_movl_T0_im((long)s->pc);        gen_op_movl_reg_TN[0][15]();        s->is_jmp = DISAS_WFI;        return 0;    }    rd = (insn >> 12) & 0xf;