IWMMXT_OP_CMP(subn, uint8_t, uint16_t, uint32_t, -)IWMMXT_OP_CMP(addn, uint8_t, uint16_t, uint32_t, +)#undef CMP/* TODO Signed- and Unsigned-Saturation */#define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((M0 >> SHR) & MASK) \            OPER (TYPE) ((M1 >> SHR) & MASK)) & MASK) << SHR)IWMMXT_OP_CMP(subu, uint8_t, uint16_t, uint32_t, -)IWMMXT_OP_CMP(addu, uint8_t, uint16_t, uint32_t, +)IWMMXT_OP_CMP(subs, int8_t, int16_t, int32_t, -)IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)#undef CMP#undef IWMMXT_OP_CMPvoid OPPROTO op_iwmmxt_avgb_M0_wRn(void){#define AVGB(SHR) ((( \        ((M0 >> SHR) & 0xff) + ((M1 >> SHR) & 0xff) + PARAM2) >> 1) << SHR)    M0 =        AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) |        AVGB(32) | AVGB(40) | AVGB(48) | AVGB(56);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        SIMD8_SET(ZBIT8((M0 >> 0) & 0xff), SIMD_ZBIT, 0) |        SIMD8_SET(ZBIT8((M0 >> 8) & 0xff), SIMD_ZBIT, 1) |        SIMD8_SET(ZBIT8((M0 >> 16) & 0xff), SIMD_ZBIT, 2) |        SIMD8_SET(ZBIT8((M0 >> 24) & 0xff), SIMD_ZBIT, 3) |        SIMD8_SET(ZBIT8((M0 >> 32) & 0xff), SIMD_ZBIT, 4) |        SIMD8_SET(ZBIT8((M0 >> 40) & 0xff), SIMD_ZBIT, 5) |        SIMD8_SET(ZBIT8((M0 >> 48) & 0xff), SIMD_ZBIT, 6) |        SIMD8_SET(ZBIT8((M0 >> 56) & 0xff), SIMD_ZBIT, 7);#undef AVGB}void OPPROTO op_iwmmxt_avgw_M0_wRn(void){#define AVGW(SHR) ((( \        ((M0 >> SHR) & 0xffff) + ((M1 >> SHR) & 0xffff) + PARAM2) >> 1) << SHR)    M0 = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        SIMD16_SET(ZBIT16((M0 >> 0) & 0xffff), SIMD_ZBIT, 0) |        SIMD16_SET(ZBIT16((M0 >> 16) & 0xffff), SIMD_ZBIT, 1) |        SIMD16_SET(ZBIT16((M0 >> 32) & 0xffff), SIMD_ZBIT, 2) |        SIMD16_SET(ZBIT16((M0 >> 48) & 0xffff), SIMD_ZBIT, 3);#undef AVGW}void OPPROTO op_iwmmxt_msadb_M0_wRn(void){    M0 = ((((M0 >> 0) & 0xffff) * ((M1 >> 0) & 0xffff) +           ((M0 >> 16) & 0xffff) * ((M1 >> 16) & 0xffff)) & 0xffffffff) |         ((((M0 >> 32) & 0xffff) * ((M1 >> 32) & 0xffff) +           ((M0 >> 48) & 0xffff) * ((M1 >> 48) & 0xffff)) << 32);}void OPPROTO op_iwmmxt_align_M0_T0_wRn(void){    M0 >>= T0 << 3;    M0 |= M1 << (64 - (T0 << 3));}void OPPROTO op_iwmmxt_insr_M0_T0_T1(void){    M0 &= ~((uint64_t) T1 << PARAM1);    M0 |= (uint64_t) (T0 & T1) << PARAM1;}void OPPROTO op_iwmmxt_extrsb_T0_M0(void){    T0 = EXTEND8((M0 >> PARAM1) & 0xff);}void OPPROTO op_iwmmxt_extrsw_T0_M0(void){    T0 = EXTEND16((M0 >> PARAM1) & 0xffff);}void OPPROTO op_iwmmxt_extru_T0_M0_T1(void){    T0 = (M0 >> PARAM1) & T1;}void OPPROTO op_iwmmxt_bcstb_M0_T0(void){    T0 &= 0xff;    M0 =        ((uint64_t) T0 << 0) | ((uint64_t) T0 << 8) |        ((uint64_t) T0 << 16) | ((uint64_t) T0 << 24) |        ((uint64_t) T0 << 32) | ((uint64_t) T0 << 40) |        ((uint64_t) T0 << 48) | ((uint64_t) T0 << 56);}void OPPROTO op_iwmmxt_bcstw_M0_T0(void){    T0 &= 0xffff;    M0 =        ((uint64_t) T0 << 0) | ((uint64_t) T0 << 16) |        ((uint64_t) T0 << 32) | ((uint64_t) T0 << 48);}void OPPROTO op_iwmmxt_bcstl_M0_T0(void){    M0 = ((uint64_t) T0 << 0) | ((uint64_t) T0 << 32);}void OPPROTO op_iwmmxt_addcb_M0(void){    M0 =        ((M0 >> 0) & 0xff) + ((M0 >> 8) & 0xff) +        ((M0 >> 16) & 0xff) + ((M0 >> 24) & 0xff) +        ((M0 >> 32) & 0xff) + ((M0 >> 40) & 0xff) +        ((M0 >> 48) & 0xff) + ((M0 >> 56) & 0xff);}void OPPROTO op_iwmmxt_addcw_M0(void){    M0 =        ((M0 >> 0) & 0xffff) + ((M0 >> 16) & 0xffff) +        ((M0 >> 32) & 0xffff) + ((M0 >> 48) & 0xffff);}void OPPROTO op_iwmmxt_addcl_M0(void){    M0 = (M0 & 0xffffffff) + (M0 >> 32);}void OPPROTO op_iwmmxt_msbb_T0_M0(void){    T0 =        ((M0 >> 7) & 0x01) | ((M0 >> 14) & 0x02) |        ((M0 >> 21) & 0x04) | ((M0 >> 28) & 0x08) |        ((M0 >> 35) & 0x10) | ((M0 >> 42) & 0x20) |        ((M0 >> 49) & 0x40) | ((M0 >> 56) & 0x80);}void OPPROTO op_iwmmxt_msbw_T0_M0(void){    T0 =        ((M0 >> 15) & 0x01) | ((M0 >> 30) & 0x02) |        ((M0 >> 45) & 0x04) | ((M0 >> 52) & 0x08);}void OPPROTO op_iwmmxt_msbl_T0_M0(void){    T0 = ((M0 >> 31) & 0x01) | ((M0 >> 62) & 0x02);}void OPPROTO op_iwmmxt_srlw_M0_T0(void){    M0 =        (((M0 & (0xffffll << 0)) >> T0) & (0xffffll << 0)) |        (((M0 & (0xffffll << 16)) >> T0) & (0xffffll << 16)) |        (((M0 & (0xffffll << 32)) >> T0) & (0xffffll << 32)) |        (((M0 & (0xffffll << 48)) >> T0) & (0xffffll << 48));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_srll_M0_T0(void){    M0 =        ((M0 & (0xffffffffll << 0)) >> T0) |        ((M0 >> T0) & (0xffffffffll << 32));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}void OPPROTO op_iwmmxt_srlq_M0_T0(void){    M0 >>= T0;    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);}void OPPROTO op_iwmmxt_sllw_M0_T0(void){    M0 =        (((M0 & (0xffffll << 0)) << T0) & (0xffffll << 0)) |        (((M0 & (0xffffll << 16)) << T0) & (0xffffll << 16)) |        (((M0 & (0xffffll << 32)) << T0) & (0xffffll << 32)) |        (((M0 & (0xffffll << 48)) << T0) & (0xffffll << 48));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_slll_M0_T0(void){    M0 =        ((M0 << T0) & (0xffffffffll << 0)) |        ((M0 & (0xffffffffll << 32)) << T0);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}void OPPROTO op_iwmmxt_sllq_M0_T0(void){    M0 <<= T0;    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);}void OPPROTO op_iwmmxt_sraw_M0_T0(void){    M0 =        ((uint64_t) ((EXTEND16(M0 >> 0) >> T0) & 0xffff) << 0) |        ((uint64_t) ((EXTEND16(M0 >> 16) >> T0) & 0xffff) << 16) |        ((uint64_t) ((EXTEND16(M0 >> 32) >> T0) & 0xffff) << 32) |        ((uint64_t) ((EXTEND16(M0 >> 48) >> T0) & 0xffff) << 48);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_sral_M0_T0(void){    M0 =        (((EXTEND32(M0 >> 0) >> T0) & 0xffffffff) << 0) |        (((EXTEND32(M0 >> 32) >> T0) & 0xffffffff) << 32);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}void OPPROTO op_iwmmxt_sraq_M0_T0(void){    M0 = (int64_t) M0 >> T0;    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);}void OPPROTO op_iwmmxt_rorw_M0_T0(void){    M0 =        ((((M0 & (0xffffll << 0)) >> T0) |          ((M0 & (0xffffll << 0)) << (16 - T0))) & (0xffffll << 0)) |        ((((M0 & (0xffffll << 16)) >> T0) |          ((M0 & (0xffffll << 16)) << (16 - T0))) & (0xffffll << 16)) |        ((((M0 & (0xffffll << 32)) >> T0) |          ((M0 & (0xffffll << 32)) << (16 - T0))) & (0xffffll << 32)) |        ((((M0 & (0xffffll << 48)) >> T0) |          ((M0 & (0xffffll << 48)) << (16 - T0))) & (0xffffll << 48));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_rorl_M0_T0(void){    M0 =        ((M0 & (0xffffffffll << 0)) >> T0) |        ((M0 >> T0) & (0xffffffffll << 32)) |        ((M0 << (32 - T0)) & (0xffffffffll << 0)) |        ((M0 & (0xffffffffll << 32)) << (32 - T0));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}void OPPROTO op_iwmmxt_rorq_M0_T0(void){    M0 = (M0 >> T0) | (M0 << (64 - T0));    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(M0);}void OPPROTO op_iwmmxt_shufh_M0_T0(void){    M0 =        (((M0 >> ((T0 << 4) & 0x30)) & 0xffff) << 0) |        (((M0 >> ((T0 << 2) & 0x30)) & 0xffff) << 16) |        (((M0 >> ((T0 << 0) & 0x30)) & 0xffff) << 32) |        (((M0 >> ((T0 >> 2) & 0x30)) & 0xffff) << 48);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}/* TODO: Unsigned-Saturation */void OPPROTO op_iwmmxt_packuw_M0_wRn(void){    M0 =        (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |        (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |        (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |        (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |        NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |        NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |        NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);}void OPPROTO op_iwmmxt_packul_M0_wRn(void){    M0 =        (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |        (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_packuq_M0_wRn(void){    M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}/* TODO: Signed-Saturation */void OPPROTO op_iwmmxt_packsw_M0_wRn(void){    M0 =        (((M0 >> 0) & 0xff) << 0) | (((M0 >> 16) & 0xff) << 8) |        (((M0 >> 32) & 0xff) << 16) | (((M0 >> 48) & 0xff) << 24) |        (((M1 >> 0) & 0xff) << 32) | (((M1 >> 16) & 0xff) << 40) |        (((M1 >> 32) & 0xff) << 48) | (((M1 >> 48) & 0xff) << 56);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT8(M0 >> 0, 0) | NZBIT8(M0 >> 8, 1) |        NZBIT8(M0 >> 16, 2) | NZBIT8(M0 >> 24, 3) |        NZBIT8(M0 >> 32, 4) | NZBIT8(M0 >> 40, 5) |        NZBIT8(M0 >> 48, 6) | NZBIT8(M0 >> 56, 7);}void OPPROTO op_iwmmxt_packsl_M0_wRn(void){    M0 =        (((M0 >> 0) & 0xffff) << 0) | (((M0 >> 32) & 0xffff) << 16) |        (((M1 >> 0) & 0xffff) << 32) | (((M1 >> 32) & 0xffff) << 48);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT16(M0 >> 0, 0) | NZBIT16(M0 >> 16, 1) |        NZBIT16(M0 >> 32, 2) | NZBIT16(M0 >> 48, 3);}void OPPROTO op_iwmmxt_packsq_M0_wRn(void){    M0 = (M0 & 0xffffffff) | ((M1 & 0xffffffff) << 32);    env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =        NZBIT32(M0 >> 0, 0) | NZBIT32(M0 >> 32, 1);}void OPPROTO op_iwmmxt_muladdsl_M0_T0_T1(void){    M0 += (int32_t) EXTEND32(T0) * (int32_t) EXTEND32(T1);}void OPPROTO op_iwmmxt_muladdsw_M0_T0_T1(void){    M0 += EXTEND32(EXTEND16S((T0 >> 0) & 0xffff) *                   EXTEND16S((T1 >> 0) & 0xffff));    M0 += EXTEND32(EXTEND16S((T0 >> 16) & 0xffff) *                   EXTEND16S((T1 >> 16) & 0xffff));}void OPPROTO op_iwmmxt_muladdswl_M0_T0_T1(void){    M0 += EXTEND32(EXTEND16S(T0 & 0xffff) *                   EXTEND16S(T1 & 0xffff));}