/*    NetWinder Floating Point Emulator    (c) Rebel.COM, 1998,1999    Direct questions, comments to Scott Bambrough <scottb@netwinder.org>    This program is free software; you can redistribute it and/or modify    it under the terms of the GNU General Public License as published by    the Free Software Foundation; either version 2 of the License, or    (at your option) any later version.    This program is distributed in the hope that it will be useful,    but WITHOUT ANY WARRANTY; without even the implied warranty of    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the    GNU General Public License for more details.    You should have received a copy of the GNU General Public License    along with this program; if not, write to the Free Software    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.*/#ifndef __FPOPCODE_H__#define __FPOPCODE_H__/*ARM Floating Point Instruction Classes| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||c o n d|1 1 0 P|U|u|W|L|   Rn  |v|  Fd |0|0|0|1|  o f f s e t  | CPDT|c o n d|1 1 0 P|U|w|W|L|   Rn  |x|  Fd |0|0|0|1|  o f f s e t  | CPDT| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ||c o n d|1 1 1 0|a|b|c|d|e|  Fn |j|  Fd |0|0|0|1|f|g|h|0|i|  Fm | CPDO|c o n d|1 1 1 0|a|b|c|L|e|  Fn |   Rd  |0|0|0|1|f|g|h|1|i|  Fm | CPRT|c o n d|1 1 1 0|a|b|c|1|e|  Fn |1|1|1|1|0|0|0|1|f|g|h|1|i|  Fm | comparisons| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |CPDT		data transfer instructions		LDF, STF, LFM, SFMCPDO		dyadic arithmetic instructions		ADF, MUF, SUF, RSF, DVF, RDF,		POW, RPW, RMF, FML, FDV, FRD, POLCPDO		monadic arithmetic instructions		MVF, MNF, ABS, RND, SQT, LOG, LGN, EXP,		SIN, COS, TAN, ASN, ACS, ATN, URD, NRMCPRT		joint arithmetic/data transfer instructions		FIX (arithmetic followed by load/store)		FLT (load/store followed by arithmetic)		CMF, CNF CMFE, CNFE (comparisons)		WFS, RFS (write/read floating point status register)		WFC, RFC (write/read floating point control register)cond		condition codesP		pre/post index bit: 0 = postindex, 1 = preindexU		up/down bit: 0 = stack grows down, 1 = stack grows upW		write back bit: 1 = update base register (Rn)L		load/store bit: 0 = store, 1 = loadRn		base registerRd		destination/source registerFd		floating point destination registerFn		floating point source registerFm		floating point source register or floating point constantuv		transfer length (TABLE 1)wx		register count (TABLE 2)abcd		arithmetic opcode (TABLES 3 & 4)ef		destination size (rounding precision) (TABLE 5)gh		rounding mode (TABLE 6)j		dyadic/monadic bit: 0 = dyadic, 1 = monadici 		constant bit: 1 = constant (TABLE 6)*//*TABLE 1+-------------------------+---+---+---------+---------+|  Precision              | u | v | FPSR.EP | length  |+-------------------------+---+---+---------+---------+| Single                  | 0