/* *  i386 emulator main execution loop * *  Copyright (c) 2003-2005 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */#include "config.h"#include "exec.h"#include "disas.h"#if !defined(CONFIG_SOFTMMU)#undef EAX#undef ECX#undef EDX#undef EBX#undef ESP#undef EBP#undef ESI#undef EDI#undef EIP#include <signal.h>#include <sys/ucontext.h>#endifint tb_invalidated_flag;//#define DEBUG_EXEC//#define DEBUG_SIGNAL#define SAVE_GLOBALS()#define RESTORE_GLOBALS()#if defined(__sparc__) && !defined(HOST_SOLARIS)#include <features.h>#if defined(__GLIBC__) && ((__GLIBC__ < 2) || \                           ((__GLIBC__ == 2) && (__GLIBC_MINOR__ <= 90)))// Work around ugly bugs in glibc that mangle global register contentsstatic volatile void *saved_env;static volatile unsigned long saved_t0, saved_i7;#undef SAVE_GLOBALS#define SAVE_GLOBALS() do {                                     \        saved_env = env;                                        \        saved_t0 = T0;                                          \        asm volatile ("st %%i7, [%0]" : : "r" (&saved_i7));     \    } while(0)#undef RESTORE_GLOBALS#define RESTORE_GLOBALS() do {                                  \        env = (void *)saved_env;                                \        T0 = saved_t0;                                          \        asm volatile ("ld [%0], %%i7" : : "r" (&saved_i7));     \    } while(0)static int sparc_setjmp(jmp_buf buf){    int ret;    SAVE_GLOBALS();    ret = setjmp(buf);    RESTORE_GLOBALS();    return ret;}#undef setjmp#define setjmp(jmp_buf) sparc_setjmp(jmp_buf)static void sparc_longjmp(jmp_buf buf, int val){    SAVE_GLOBALS();    longjmp(buf, val);}#define longjmp(jmp_buf, val) sparc_longjmp(jmp_buf, val)#endif#endifvoid cpu_loop_exit(void){    /* NOTE: the register at this point must be saved by hand because       longjmp restore them */    regs_to_env();    longjmp(env->jmp_env, 1);}#if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))#define reg_T2#endif/* exit the current TB from a signal handler. The host registers are   restored in a state compatible with the CPU emulator */void cpu_resume_from_signal(CPUState *env1, void *puc){#if !defined(CONFIG_SOFTMMU)    struct ucontext *uc = puc;#endif    env = env1;    /* XXX: restore cpu registers saved in host registers */#if !defined(CONFIG_SOFTMMU)    if (puc) {        /* XXX: use siglongjmp ? */        sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);    }#endif    longjmp(env->jmp_env, 1);}static TranslationBlock *tb_find_slow(target_ulong pc,                                      target_ulong cs_base,                                      uint64_t flags){    TranslationBlock *tb, **ptb1;    int code_gen_size;    unsigned int h;    target_ulong phys_pc, phys_page1, phys_page2, virt_page2;    uint8_t *tc_ptr;    spin_lock(&tb_lock);    tb_invalidated_flag = 0;    regs_to_env(); /* XXX: do it just before cpu_gen_code() */    /* find translated block using physical mappings */    phys_pc = get_phys_addr_code(env, pc);    phys_page1 = phys_pc & TARGET_PAGE_MASK;    phys_page2 = -1;    h = tb_phys_hash_func(phys_pc);    ptb1 = &tb_phys_hash[h];    for(;;) {        tb = *ptb1;        if (!tb)            goto not_found;        if (tb->pc == pc &&            tb->page_addr[0] == phys_page1 &&            tb->cs_base == cs_base &&            tb->flags == flags) {            /* check next page if needed */            if (tb->page_addr[1] != -1) {                virt_page2 = (pc & TARGET_PAGE_MASK) +                    TARGET_PAGE_SIZE;                phys_page2 = get_phys_addr_code(env, virt_page2);                if (tb->page_addr[1] == phys_page2)                    goto found;            } else {                goto found;            }        }        ptb1 = &tb->phys_hash_next;    } not_found:    /* if no translated code available, then translate it now */    tb = tb_alloc(pc);    if (!tb) {        /* flush must be done */        tb_flush(env);        /* cannot fail at this point */        tb = tb_alloc(pc);        /* don't forget to invalidate previous TB info */        tb_invalidated_flag = 1;    }    tc_ptr = code_gen_ptr;    tb->tc_ptr = tc_ptr;    tb->cs_base = cs_base;    tb->flags = flags;    SAVE_GLOBALS();    cpu_gen_code(env, tb, &code_gen_size);    RESTORE_GLOBALS();    code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));    /* check next page if needed */    virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;    phys_page2 = -1;    if ((pc & TARGET_PAGE_MASK) != virt_page2) {        phys_page2 = get_phys_addr_code(env, virt_page2);    }    tb_link_phys(tb, phys_pc, phys_page2); found:    /* we add the TB in the virtual pc hash table */    env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;    spin_unlock(&tb_lock);    return tb;}static inline TranslationBlock *tb_find_fast(void){    TranslationBlock *tb;    target_ulong cs_base, pc;    uint64_t flags;    /* we record a subset of the CPU state. It will       always be the same before a given translated block       is executed. */#if defined(TARGET_I386)    flags = env->hflags;    flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));    flags |= env->intercept;    cs_base = env->segs[R_CS].base;    pc = cs_base + env->eip;#elif defined(TARGET_ARM)    flags = env->thumb | (env->vfp.vec_len << 1)            | (env->vfp.vec_stride << 4);    if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)        flags |= (1 << 6);    if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))        flags |= (1 << 7);    flags |= (env->condexec_bits << 8);    cs_base = 0;    pc = env->regs[15];#elif defined(TARGET_SPARC)#ifdef TARGET_SPARC64    // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled    flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))        | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);#else    // FPU enable . Supervisor    flags = (env->psref << 4) | env->psrs;#endif    cs_base = env->npc;    pc = env->pc;#elif defined(TARGET_PPC)    flags = env->hflags;    cs_base = 0;    pc = env->nip;#elif defined(TARGET_MIPS)    flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);    cs_base = 0;    pc = env->PC[env->current_tc];#elif defined(TARGET_M68K)    flags = (env->fpcr & M68K_FPCR_PREC)  /* Bit  6 */            | (env->sr & SR_S)            /* Bit  13 */            | ((env->macsr >> 4) & 0xf);  /* Bits 0-3 */    cs_base = 0;    pc = env->pc;#elif defined(TARGET_SH4)    flags = env->flags;    cs_base = 0;    pc = env->pc;#elif defined(TARGET_ALPHA)    flags = env->ps;    cs_base = 0;    pc = env->pc;#elif defined(TARGET_CRIS)    flags = 0;    cs_base = 0;    pc = env->pc;#else#error unsupported CPU#endif    tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];    if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||                         tb->flags != flags, 0)) {        tb = tb_find_slow(pc, cs_base, flags);        /* Note: we do it here to avoid a gcc bug on Mac OS X when           doing it in tb_find_slow */        if (tb_invalidated_flag) {            /* as some TB could have been invalidated because               of memory exceptions while generating the code, we               must recompute the hash index here */            T0 = 0;        }    }    return tb;}#define BREAK_CHAIN T0 = 0/* main execution loop */int cpu_exec(CPUState *env1){#define DECLARE_HOST_REGS 1#include "hostregs_helper.h"#if defined(TARGET_SPARC)#if defined(reg_REGWPTR)    uint32_t *saved_regwptr;#endif#endif    int ret, interrupt_request;    void (*gen_func)(void);    TranslationBlock *tb;    uint8_t *tc_ptr;    if (cpu_halted(env1) == EXCP_HALTED)        return EXCP_HALTED;    cpu_single_env = env1;    /* first we save global registers */#define SAVE_HOST_REGS 1#include "hostregs_helper.h"    env = env1;    SAVE_GLOBALS();    env_to_regs();#if defined(TARGET_I386)    /* put eflags in CPU temporary format */    CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);    DF = 1 - (2 * ((env->eflags >> 10) & 1));    CC_OP = CC_OP_EFLAGS;    env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);#elif defined(TARGET_SPARC)#if defined(reg_REGWPTR)    saved_regwptr = REGWPTR;#endif#elif defined(TARGET_M68K)    env->cc_op = CC_OP_FLAGS;    env->cc_dest = env->sr & 0xf;    env->cc_x = (env->sr >> 4) & 1;#elif defined(TARGET_ALPHA)#elif defined(TARGET_ARM)#elif defined(TARGET_PPC)#elif defined(TARGET_MIPS)#elif defined(TARGET_SH4)#elif defined(TARGET_CRIS)    /* XXXXX */#else#error unsupported target CPU#endif    env->exception_index = -1;    /* prepare setjmp context for exception handling */    for(;;) {        if (setjmp(env->jmp_env) == 0) {            env->current_tb = NULL;            /* if an exception is pending, we execute it here */            if (env->exception_index >= 0) {                if (env->exception_index >= EXCP_INTERRUPT) {                    /* exit request from the cpu execution loop */                    ret = env->exception_index;                    break;                } else if (env->user_mode_only) {                    /* if user mode only, we simulate a fake exception                       which will be handled outside the cpu execution                       loop */#if defined(TARGET_I386)                    do_interrupt_user(env->exception_index,                                      env->exception_is_int,                                      env->error_code,                                      env->exception_next_eip);#endif                    ret = env->exception_index;                    break;                } else {#if defined(TARGET_I386)                    /* simulate a real cpu exception. On i386, it can                       trigger new exceptions, but we do not handle                       double or triple faults yet. */                    do_interrupt(env->exception_index,                                 env->exception_is_int,                                 env->error_code,                                 env->exception_next_eip, 0);                    /* successfully delivered */                    env->old_exception = -1;#elif defined(TARGET_PPC)                    do_interrupt(env);#elif defined(TARGET_MIPS)                    do_interrupt(env);