/* see if it is an MMU fault */    ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);    if (ret < 0)        return 0; /* not an MMU fault */    if (ret == 0)        return 1; /* the MMU fault was handled without causing real CPU fault */    /* now we have a real cpu fault */    tb = tb_find_pc(pc);    if (tb) {        /* the PC is inside the translated code. It means that we have           a virtual CPU fault */        cpu_restore_state(tb, env, pc, puc);    }#if 0        printf("PF exception: NIP=0x%08x error=0x%x %p\n",               env->nip, env->error_code, tb);#endif    /* we restore the process signal mask as the sigreturn should       do it (XXX: use sigsetjmp) */    sigprocmask(SIG_SETMASK, old_set, NULL);    cpu_loop_exit();    /* never comes here */    return 1;}#elif defined (TARGET_CRIS)static inline int handle_cpu_signal(unsigned long pc, unsigned long address,                                    int is_write, sigset_t *old_set,                                    void *puc){    TranslationBlock *tb;    int ret;    if (cpu_single_env)        env = cpu_single_env; /* XXX: find a correct solution for multithread */#if defined(DEBUG_SIGNAL)    printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",           pc, address, is_write, *(unsigned long *)old_set);#endif    /* XXX: locking issue */    if (is_write && page_unprotect(h2g(address), pc, puc)) {        return 1;    }    /* see if it is an MMU fault */    ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);    if (ret < 0)        return 0; /* not an MMU fault */    if (ret == 0)        return 1; /* the MMU fault was handled without causing real CPU fault */    /* now we have a real cpu fault */    tb = tb_find_pc(pc);    if (tb) {        /* the PC is inside the translated code. It means that we have           a virtual CPU fault */        cpu_restore_state(tb, env, pc, puc);    }#if 0        printf("PF exception: NIP=0x%08x error=0x%x %p\n",               env->nip, env->error_code, tb);#endif    /* we restore the process signal mask as the sigreturn should       do it (XXX: use sigsetjmp) */    sigprocmask(SIG_SETMASK, old_set, NULL);    cpu_loop_exit();    /* never comes here */    return 1;}#else#error unsupported target CPU#endif#if defined(__i386__)#if defined(__APPLE__)# include <sys/ucontext.h># define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext->ss.eip))# define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)# define ERROR_sig(context)   ((context)->uc_mcontext->es.err)#else# define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])# define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])# define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])#endifint cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    int trapno;#ifndef REG_EIP/* for glibc 2.1 */#define REG_EIP    EIP#define REG_ERR    ERR#define REG_TRAPNO TRAPNO#endif    pc = EIP_sig(uc);    trapno = TRAP_sig(uc);    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             trapno == 0xe ?                             (ERROR_sig(uc) >> 1) & 1 : 0,                             &uc->uc_sigmask, puc);}#elif defined(__x86_64__)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    pc = uc->uc_mcontext.gregs[REG_RIP];    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?                             (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,                             &uc->uc_sigmask, puc);}#elif defined(__powerpc__)/*********************************************************************** * signal context platform-specific definitions * From Wine */#ifdef linux/* All Registers access - only for local access */# define REG_sig(reg_name, context)		((context)->uc_mcontext.regs->reg_name)/* Gpr Registers access  */# define GPR_sig(reg_num, context)		REG_sig(gpr[reg_num], context)# define IAR_sig(context)			REG_sig(nip, context)	/* Program counter */# define MSR_sig(context)			REG_sig(msr, context)   /* Machine State Register (Supervisor) */# define CTR_sig(context)			REG_sig(ctr, context)   /* Count register */# define XER_sig(context)			REG_sig(xer, context) /* User's integer exception register */# define LR_sig(context)			REG_sig(link, context) /* Link register */# define CR_sig(context)			REG_sig(ccr, context) /* Condition register *//* Float Registers access  */# define FLOAT_sig(reg_num, context)		(((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])# define FPSCR_sig(context)			(*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))/* Exception Registers access */# define DAR_sig(context)			REG_sig(dar, context)# define DSISR_sig(context)			REG_sig(dsisr, context)# define TRAP_sig(context)			REG_sig(trap, context)#endif /* linux */#ifdef __APPLE__# include <sys/ucontext.h>typedef struct ucontext SIGCONTEXT;/* All Registers access - only for local access */# define REG_sig(reg_name, context)		((context)->uc_mcontext->ss.reg_name)# define FLOATREG_sig(reg_name, context)	((context)->uc_mcontext->fs.reg_name)# define EXCEPREG_sig(reg_name, context)	((context)->uc_mcontext->es.reg_name)# define VECREG_sig(reg_name, context)		((context)->uc_mcontext->vs.reg_name)/* Gpr Registers access */# define GPR_sig(reg_num, context)		REG_sig(r##reg_num, context)# define IAR_sig(context)			REG_sig(srr0, context)	/* Program counter */# define MSR_sig(context)			REG_sig(srr1, context)  /* Machine State Register (Supervisor) */# define CTR_sig(context)			REG_sig(ctr, context)# define XER_sig(context)			REG_sig(xer, context) /* Link register */# define LR_sig(context)			REG_sig(lr, context)  /* User's integer exception register */# define CR_sig(context)			REG_sig(cr, context)  /* Condition register *//* Float Registers access */# define FLOAT_sig(reg_num, context)		FLOATREG_sig(fpregs[reg_num], context)# define FPSCR_sig(context)			((double)FLOATREG_sig(fpscr, context))/* Exception Registers access */# define DAR_sig(context)			EXCEPREG_sig(dar, context)     /* Fault registers for coredump */# define DSISR_sig(context)			EXCEPREG_sig(dsisr, context)# define TRAP_sig(context)			EXCEPREG_sig(exception, context) /* number of powerpc exception taken */#endif /* __APPLE__ */int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    int is_write;    pc = IAR_sig(uc);    is_write = 0;#if 0    /* ppc 4xx case */    if (DSISR_sig(uc) & 0x00800000)        is_write = 1;#else    if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))        is_write = 1;#endif    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write, &uc->uc_sigmask, puc);}#elif defined(__alpha__)int cpu_signal_handler(int host_signum, void *pinfo,                           void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    uint32_t *pc = uc->uc_mcontext.sc_pc;    uint32_t insn = *pc;    int is_write = 0;    /* XXX: need kernel patch to get write flag faster */    switch (insn >> 26) {    case 0x0d: // stw    case 0x0e: // stb    case 0x0f: // stq_u    case 0x24: // stf    case 0x25: // stg    case 0x26: // sts    case 0x27: // stt    case 0x2c: // stl    case 0x2d: // stq    case 0x2e: // stl_c    case 0x2f: // stq_c	is_write = 1;    }    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write, &uc->uc_sigmask, puc);}#elif defined(__sparc__)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    uint32_t *regs = (uint32_t *)(info + 1);    void *sigmask = (regs + 20);    unsigned long pc;    int is_write;    uint32_t insn;    /* XXX: is there a standard glibc define ? */    pc = regs[1];    /* XXX: need kernel patch to get write flag faster */    is_write = 0;    insn = *(uint32_t *)pc;    if ((insn >> 30) == 3) {      switch((insn >> 19) & 0x3f) {      case 0x05: // stb      case 0x06: // sth      case 0x04: // st      case 0x07: // std      case 0x24: // stf      case 0x27: // stdf      case 0x25: // stfsr	is_write = 1;	break;      }    }    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write, sigmask, NULL);}#elif defined(__arm__)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    int is_write;    pc = uc->uc_mcontext.gregs[R15];    /* XXX: compute is_write */    is_write = 0;    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write,                             &uc->uc_sigmask, puc);}#elif defined(__mc68000)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    int is_write;    pc = uc->uc_mcontext.gregs[16];    /* XXX: compute is_write */    is_write = 0;    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write,                             &uc->uc_sigmask, puc);}#elif defined(__ia64)#ifndef __ISR_VALID  /* This ought to be in <bits/siginfo.h>... */# define __ISR_VALID	1#endifint cpu_signal_handler(int host_signum, void *pinfo, void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long ip;    int is_write = 0;    ip = uc->uc_mcontext.sc_ip;    switch (host_signum) {      case SIGILL:      case SIGFPE:      case SIGSEGV:      case SIGBUS:      case SIGTRAP:	  if (info->si_code && (info->si_segvflags & __ISR_VALID))	      /* ISR.W (write-access) is bit 33:  */	      is_write = (info->si_isr >> 33) & 1;	  break;      default:	  break;    }    return handle_cpu_signal(ip, (unsigned long)info->si_addr,                             is_write,                             &uc->uc_sigmask, puc);}#elif defined(__s390__)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    unsigned long pc;    int is_write;    pc = uc->uc_mcontext.psw.addr;    /* XXX: compute is_write */    is_write = 0;    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write, &uc->uc_sigmask, puc);}#elif defined(__mips__)int cpu_signal_handler(int host_signum, void *pinfo,                       void *puc){    siginfo_t *info = pinfo;    struct ucontext *uc = puc;    greg_t pc = uc->uc_mcontext.pc;    int is_write;    /* XXX: compute is_write */    is_write = 0;    return handle_cpu_signal(pc, (unsigned long)info->si_addr,                             is_write, &uc->uc_sigmask, puc);}#else#error host CPU specific signal handler needed#endif#endif /* !defined(CONFIG_SOFTMMU) */