/* This file is composed of several different files from the upstream   sourceware.org CVS.  Original file boundaries marked with **** */#include <string.h>#include <math.h>#include <stdio.h>#include "dis-asm.h"/* **** foatformat.h from sourceware.org CVS 2005-08-14.  *//* IEEE floating point support declarations, for GDB, the GNU Debugger.   Copyright 1991, 1994, 1995, 1997, 2000, 2003 Free Software Foundation, Inc.This file is part of GDB.This program is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2 of the License, or(at your option) any later version.This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with this program; if not, write to the Free SoftwareFoundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */#if !defined (FLOATFORMAT_H)#define FLOATFORMAT_H 1/*#include "ansidecl.h" *//* A floatformat consists of a sign bit, an exponent and a mantissa.  Once the   bytes are concatenated according to the byteorder flag, then each of those   fields is contiguous.  We number the bits with 0 being the most significant   (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field   contains with the *_start and *_len fields.  *//* What is the order of the bytes. */enum floatformat_byteorders {  /* Standard little endian byte order.     EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */  floatformat_little,  /* Standard big endian byte order.     EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */  floatformat_big,  /* Little endian byte order but big endian word order.     EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */  floatformat_littlebyte_bigword};enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };struct floatformat{  enum floatformat_byteorders byteorder;  unsigned int totalsize;	/* Total size of number in bits */  /* Sign bit is always one bit long.  1 means negative, 0 means positive.  */  unsigned int sign_start;  unsigned int exp_start;  unsigned int exp_len;  /* Bias added to a "true" exponent to form the biased exponent.  It     is intentionally signed as, otherwize, -exp_bias can turn into a     very large number (e.g., given the exp_bias of 0x3fff and a 64     bit long, the equation (long)(1 - exp_bias) evaluates to     4294950914) instead of -16382).  */  int exp_bias;  /* Exponent value which indicates NaN.  This is the actual value stored in     the float, not adjusted by the exp_bias.  This usually consists of all     one bits.  */  unsigned int exp_nan;  unsigned int man_start;  unsigned int man_len;  /* Is the integer bit explicit or implicit?  */  enum floatformat_intbit intbit;  /* Internal name for debugging. */  const char *name;  /* Validator method.  */  int (*is_valid) (const struct floatformat *fmt, const char *from);};/* floatformats for IEEE single and double, big and little endian.  */extern const struct floatformat floatformat_ieee_single_big;extern const struct floatformat floatformat_ieee_single_little;extern const struct floatformat floatformat_ieee_double_big;extern const struct floatformat floatformat_ieee_double_little;/* floatformat for ARM IEEE double, little endian bytes and big endian words */extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;/* floatformats for various extendeds.  */extern const struct floatformat floatformat_i387_ext;extern const struct floatformat floatformat_m68881_ext;extern const struct floatformat floatformat_i960_ext;extern const struct floatformat floatformat_m88110_ext;extern const struct floatformat floatformat_m88110_harris_ext;extern const struct floatformat floatformat_arm_ext_big;extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;/* IA-64 Floating Point register spilt into memory.  */extern const struct floatformat floatformat_ia64_spill_big;extern const struct floatformat floatformat_ia64_spill_little;extern const struct floatformat floatformat_ia64_quad_big;extern const struct floatformat floatformat_ia64_quad_little;/* Convert from FMT to a double.   FROM is the address of the extended float.   Store the double in *TO.  */extern voidfloatformat_to_double (const struct floatformat *, const char *, double *);/* The converse: convert the double *FROM to FMT   and store where TO points.  */extern voidfloatformat_from_double (const struct floatformat *, const double *, char *);/* Return non-zero iff the data at FROM is a valid number in format FMT.  */extern intfloatformat_is_valid (const struct floatformat *fmt, const char *from);#endif	/* defined (FLOATFORMAT_H) *//* **** End of floatformat.h *//* **** m68k-dis.h from sourceware.org CVS 2005-08-14.  *//* Opcode table header for m680[01234]0/m6888[12]/m68851.   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,   2003, 2004 Free Software Foundation, Inc.   This file is part of GDB, GAS, and the GNU binutils.   GDB, GAS, and the GNU binutils are free software; you can redistribute   them and/or modify them under the terms of the GNU General Public   License as published by the Free Software Foundation; either version   1, or (at your option) any later version.   GDB, GAS, and the GNU binutils are distributed in the hope that they   will be useful, but WITHOUT ANY WARRANTY; without even the implied   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See   the GNU General Public License for more details.   You should have received a copy of the GNU General Public License   along with this file; see the file COPYING.  If not, write to the Free   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA   02110-1301, USA.  *//* These are used as bit flags for the arch field in the m68k_opcode   structure.  */#define	_m68k_undef  0#define	m68000   0x001#define	m68008   m68000 /* Synonym for -m68000.  otherwise unused.  */#define	m68010   0x002#define	m68020   0x004#define	m68030   0x008#define m68ec030 m68030 /* Similar enough to -m68030 to ignore differences;			   gas will deal with the few differences.  */#define	m68040   0x010/* There is no 68050.  */#define m68060   0x020#define	m68881   0x040#define	m68882   m68881 /* Synonym for -m68881.  otherwise unused.  */#define	m68851   0x080#define cpu32	 0x100		/* e.g., 68332 */#define mcfmac   0x200		/* ColdFire MAC. */#define mcfemac  0x400		/* ColdFire EMAC. */#define cfloat   0x800		/* ColdFire FPU.  */#define mcfhwdiv 0x1000		/* ColdFire hardware divide.  */#define mcfisa_a 0x2000		/* ColdFire ISA_A.  */#define mcfisa_aa 0x4000	/* ColdFire ISA_A+.  */#define mcfisa_b 0x8000		/* ColdFire ISA_B.  */#define mcfusp   0x10000	/* ColdFire USP instructions.  */#define mcf5200  0x20000#define mcf5206e 0x40000#define mcf521x  0x80000#define mcf5249  0x100000#define mcf528x  0x200000#define mcf5307  0x400000#define mcf5407  0x800000#define mcf5470  0x1000000#define mcf5480  0x2000000 /* Handy aliases.  */#define	m68040up   (m68040 | m68060)#define	m68030up   (m68030 | m68040up)#define	m68020up   (m68020 | m68030up)#define	m68010up   (m68010 | cpu32 | m68020up)#define	m68000up   (m68000 | m68010up)#define	mfloat  (m68881 | m68882 | m68040 | m68060)#define	mmmu    (m68851 | m68030 | m68040 | m68060)/* The structure used to hold information for an opcode.  */struct m68k_opcode{  /* The opcode name.  */  const char *name;  /* The pseudo-size of the instruction(in bytes).  Used to determine     number of bytes necessary to disassemble the instruction.  */  unsigned int size;  /* The opcode itself.  */  unsigned long opcode;  /* The mask used by the disassembler.  */  unsigned long match;  /* The arguments.  */  const char *args;  /* The architectures which support this opcode.  */  unsigned int arch;};/* The structure used to hold information for an opcode alias.  */struct m68k_opcode_alias{  /* The alias name.  */  const char *alias;  /* The instruction for which this is an alias.  */  const char *primary;};/* We store four bytes of opcode for all opcodes because that is the   most any of them need.  The actual length of an instruction is   always at least 2 bytes, and is as much longer as necessary to hold   the operands it has.   The match field is a mask saying which bits must match particular   opcode in order for an instruction to be an instance of that   opcode.   The args field is a string containing two characters for each   operand of the instruction.  The first specifies the kind of   operand; the second, the place it is stored.  *//* Kinds of operands:   Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-   D  data register only.  Stored as 3 bits.   A  address register only.  Stored as 3 bits.   a  address register indirect only.  Stored as 3 bits.   R  either kind of register.  Stored as 4 bits.   r  either kind of register indirect only.  Stored as 4 bits.      At the moment, used only for cas2 instruction.   F  floating point coprocessor register only.   Stored as 3 bits.   O  an offset (or width): immediate data 0-31 or data register.      Stored as 6 bits in special format for BF... insns.   +  autoincrement only.  Stored as 3 bits (number of the address register).   -  autodecrement only.  Stored as 3 bits (number of the address register).   Q  quick immediate data.  Stored as 3 bits.      This matches an immediate operand only when value is in range 1 .. 8.   M  moveq immediate data.  Stored as 8 bits.      This matches an immediate operand only when value is in range -128..127   T  trap vector immediate data.  Stored as 4 bits.   k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or      a three bit register offset, depending on the field type.   #  immediate data.  Stored in special places (b, w or l)      which say how many bits to store.   ^  immediate data for floating point instructions.   Special places      are offset by 2 bytes from '#'...   B  pc-relative address, converted to an offset      that is treated as immediate data.   d  displacement and register.  Stores the register as 3 bits      and stores the displacement in the entire second word.   C  the CCR.  No need to store it; this is just for filtering validity.   S  the SR.  No need to store, just as with CCR.   U  the USP.  No need to store, just as with CCR.   E  the MAC ACC.  No need to store, just as with CCR.   e  the EMAC ACC[0123].   G  the MAC/EMAC MACSR.  No need to store, just as with CCR.   g  the EMAC ACCEXT{01,23}.   H  the MASK.  No need to store, just as with CCR.   i  the MAC/EMAC scale factor.   I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always      extracted from the 'd' field of word one, which means that an extended      coprocessor opcode can be skipped using the 'i' place, if needed.   s  System Control register for the floating point coprocessor.   J  Misc register for movec instruction, stored in 'j' format.	Possible values:	0x000	SFC	Source Function Code reg	[60, 40, 30, 20, 10]	0x001	DFC	Data Function Code reg		[60, 40, 30, 20, 10]	0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]	0x003	TC	MMU Translation Control		[60, 40]	0x004	ITT0	Instruction Transparent				Translation reg 0	[60, 40]	0x005	ITT1	Instruction Transparent				Translation reg 1	[60, 40]	0x006	DTT0	Data Transparent				Translation reg 0	[60, 40]	0x007	DTT1	Data Transparent				Translation reg 1	[60, 40]	0x008	BUSCR	Bus Control Register		[60]	0x800	USP	User Stack Pointer		[60, 40, 30, 20, 10]        0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]	0x802	CAAR	Cache Address Register		[        30, 20]	0x803	MSP	Master Stack Pointer		[    40, 30, 20]	0x804	ISP	Interrupt Stack Pointer		[    40, 30, 20]	0x805	MMUSR	MMU Status reg			[    40]	0x806	URP	User Root Pointer		[60, 40]	0x807	SRP	Supervisor Root Pointer		[60, 40]	0x808	PCR	Processor Configuration reg	[60]	0xC00	ROMBAR	ROM Base Address Register	[520X]	0xC04	RAMBAR0	RAM Base Address Register 0	[520X]	0xC05	RAMBAR1	RAM Base Address Register 0	[520X]	0xC0F	MBAR0	RAM Base Address Register 0	[520X]        0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]        0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]    L  Register list of the type d0-d7/a0-a7 etc.       (New!  Improved!  Can also hold fp0-fp7, as well!)       The assembler tries to see if the registers match the insn by       looking at where the insn wants them stored.    l  Register list like L, but with all the bits reversed.       Used for going the other way. . .    c  cache identifier which may be "nc" for no cache, "ic"       for instruction cache, "dc" for data cache, or "bc"       for both caches.  Used in cinv and cpush.  Always       stored in position "d".    u  Any register, with ``upper'' or ``lower'' specification.  Used       in the mac instructions with size word. The remainder are all stored as 6 bits using an address mode and a register number; they differ in which addressing modes they match.   *  all					(modes 0-6,7.0-4)   ~  alterable memory				(modes 2-6,7.0,7.1)   						(not 0,1,7.2-4)   %  alterable					(modes 0-6,7.0,7.1)						(not 7.2-4)   ;  data					(modes 0,2-6,7.0-4)						(not 1)   @  data, but not immediate			(modes 0,2-6,7.0-3)						(not 1,7.4)   !  control					(modes 2,5,6,7.0-3)						(not 0,1,3,4,7.4)   &  alterable control				(modes 2,5,6,7.0,7.1)						(not 0,1,3,4,7.2-4)   $  alterable data				(modes 0,2-6,7.0,7.1)						(not 1,7.2-4)   ?  alterable control, or data register	(modes 0,2,5,6,7.0,7.1)						(not 1,3,4,7.2-4)   /  control, or data register			(modes 0,2,5,6,7.0-3)						(not 1,3,4,7.4)   >  *save operands				(modes 2,4,5,6,7.0,7.1)						(not 0,1,3,7.2-4)   <  *restore operands				(modes 2,3,5,6,7.0-3)						(not 0,1,4,7.4)   coldfire move operands:   m  						(modes 0-4)   n						(modes 5,7.2)   o						(modes 6,7.0,7.1,7.3,7.4)   p						(modes 0-5)   coldfire bset/bclr/btst/mulsl/mulul operands:   q						(modes 0,2-5)   v						(modes 0,2-5,7.0,7.1)   b                                            (modes 0,2-5,7.2)   w                                            (modes 2-5,7.2)   y						(modes 2,5)   z						(modes 2,5,7.2)   x  mov3q immediate operand.   4						(modes 2,3,4,5)  *//* For the 68851:  *//* I didn't use much imagination in choosing the   following codes, so many of them aren't very   mnemonic. -rab   0  32 bit pmmu register	Possible values:	000	TC	Translation Control Register (68030, 68851)   1  16 bit pmmu register	111	AC	Access Control (68851)   2  8 bit pmmu register	100	CAL	Current Access Level (68851)	101	VAL	Validate Access Level (68851)	110	SCC	Stack Change Control (68851)   3  68030-only pmmu registers (32 bit)	010	TT0	Transparent Translation reg 0			(aka Access Control reg 0 -- AC0 -- on 68ec030)	011	TT1	Transparent Translation reg 1			(aka Access Control reg 1 -- AC1 -- on 68ec030)   W  wide pmmu registers	Possible values:	001	DRP	Dma Root Pointer (68851)	010	SRP	Supervisor Root Pointer (68030, 68851)	011	CRP	Cpu Root Pointer (68030, 68851)   f	function code register (68030, 68851)	0	SFC	1	DFC   V	VAL register only (68851)   X	BADx, BACx (16 bit)	100	BAD	Breakpoint Acknowledge Data (68851)	101	BAC	Breakpoint Acknowledge Control (68851)   Y	PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)   Z	PCSR (68851)   |	memory 		(modes 2-6, 7.*)