if (d[0] == '#')	{	  if (d[1] == 'l' && p - buffer < 6)	    p = buffer + 6;	  else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8')	    p = buffer + 4;	}      if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4)	p = buffer + 4;      switch (d[1])	{	case '1':	case '2':	case '3':	case '7':	case '8':	case '9':	case 'i':	  if (p - buffer < 4)	    p = buffer + 4;	  break;	case '4':	case '5':	case '6':	  if (p - buffer < 6)	    p = buffer + 6;	  break;	default:	  break;	}    }  /* pflusha is an exceptions.  It takes no arguments but is two words     long.  Recognize it by looking at the lower 16 bits of the mask.  */  if (p - buffer < 4 && (best->match & 0xFFFF) != 0)    p = buffer + 4;  /* lpstop is another exception.  It takes a one word argument but is     three words long.  */  if (p - buffer < 6      && (best->match & 0xffff) == 0xffff      && best->args[0] == '#'      && best->args[1] == 'w')    {      /* Copy the one word argument into the usual location for a one	 word argument, to simplify printing it.  We can get away with	 this because we know exactly what the second word is, and we	 aren't going to print anything based on it.  */      p = buffer + 6;      FETCH_DATA (info, p);      buffer[2] = buffer[4];      buffer[3] = buffer[5];    }  FETCH_DATA (info, p);  d = best->args;  save_p = p;  info->print_address_func = dummy_print_address;  info->fprintf_func = (fprintf_ftype) dummy_printer;  /* We scan the operands twice.  The first time we don't print anything,     but look for errors.  */  for (; *d; d += 2)    {      int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);      if (eaten >= 0)	p += eaten;      else if (eaten == -1)	{	  info->fprintf_func = save_printer;	  info->print_address_func = save_print_address;	  return 0;	}      else	{	  info->fprintf_func (info->stream,			      /* xgettext:c-format */			      _("<internal error in opcode table: %s %s>\n"),			      best->name,  best->args);	  info->fprintf_func = save_printer;	  info->print_address_func = save_print_address;	  return 2;	}    }  p = save_p;  info->fprintf_func = save_printer;  info->print_address_func = save_print_address;  d = best->args;  info->fprintf_func (info->stream, "%s", best->name);  if (*d)    info->fprintf_func (info->stream, " ");  while (*d)    {      p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info);      d += 2;      if (*d && *(d - 2) != 'I' && *d != 'k')	info->fprintf_func (info->stream, ",");    }  return p - buffer;}/* Print the m68k instruction at address MEMADDR in debugged memory,   on INFO->STREAM.  Returns length of the instruction, in bytes.  */intprint_insn_m68k (bfd_vma memaddr, disassemble_info *info){  int i;  const char *d;  unsigned int arch_mask;  struct private priv;  bfd_byte *buffer = priv.the_buffer;  int major_opcode;  static int numopcodes[16];  static const struct m68k_opcode **opcodes[16];  int val;  if (!opcodes[0])    {      /* Speed up the matching by sorting the opcode	 table on the upper four bits of the opcode.  */      const struct m68k_opcode **opc_pointer[16];      /* First count how many opcodes are in each of the sixteen buckets.  */      for (i = 0; i < m68k_numopcodes; i++)	numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++;      /* Then create a sorted table of pointers	 that point into the unsorted table.  */      opc_pointer[0] = malloc (sizeof (struct m68k_opcode *)                               * m68k_numopcodes);      opcodes[0] = opc_pointer[0];      for (i = 1; i < 16; i++)	{	  opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1];	  opcodes[i] = opc_pointer[i];	}      for (i = 0; i < m68k_numopcodes; i++)	*opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i];    }  info->private_data = (PTR) &priv;  /* Tell objdump to use two bytes per chunk     and six bytes per line for displaying raw data.  */  info->bytes_per_chunk = 2;  info->bytes_per_line = 6;  info->display_endian = BFD_ENDIAN_BIG;  priv.max_fetched = priv.the_buffer;  priv.insn_start = memaddr;  if (setjmp (priv.bailout) != 0)    /* Error return.  */    return -1;  switch (info->mach)    {    default:    case 0:      arch_mask = (unsigned int) -1;      break;    case bfd_mach_m68000:      arch_mask = m68000|m68881|m68851;      break;    case bfd_mach_m68008:      arch_mask = m68008|m68881|m68851;      break;    case bfd_mach_m68010:      arch_mask = m68010|m68881|m68851;      break;    case bfd_mach_m68020:      arch_mask = m68020|m68881|m68851;      break;    case bfd_mach_m68030:      arch_mask = m68030|m68881|m68851;      break;    case bfd_mach_m68040:      arch_mask = m68040|m68881|m68851;      break;    case bfd_mach_m68060:      arch_mask = m68060|m68881|m68851;      break;    case bfd_mach_mcf5200:      arch_mask = mcfisa_a;      break;    case bfd_mach_mcf521x:    case bfd_mach_mcf528x:      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp|mcfemac;      break;    case bfd_mach_mcf5206e:      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;      break;    case bfd_mach_mcf5249:      arch_mask = mcfisa_a|mcfhwdiv|mcfemac;      break;    case bfd_mach_mcf5307:      arch_mask = mcfisa_a|mcfhwdiv|mcfmac;      break;    case bfd_mach_mcf5407:      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac;      break;    case bfd_mach_mcf547x:    case bfd_mach_mcf548x:    case bfd_mach_mcfv4e:      arch_mask = mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp|cfloat|mcfemac;      break;    }  FETCH_DATA (info, buffer + 2);  major_opcode = (buffer[0] >> 4) & 15;  for (i = 0; i < numopcodes[major_opcode]; i++)    {      const struct m68k_opcode *opc = opcodes[major_opcode][i];      unsigned long opcode = opc->opcode;      unsigned long match = opc->match;      if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24)))	  && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16)))	  /* Only fetch the next two bytes if we need to.  */	  && (((0xffff & match) == 0)	      ||	      (FETCH_DATA (info, buffer + 4)	       && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8)))	       && ((0xff & buffer[3] & match) == (0xff & opcode)))	      )	  && (opc->arch & arch_mask) != 0)	{	  /* Don't use for printout the variants of divul and divsl	     that have the same register number in two places.	     The more general variants will match instead.  */	  for (d = opc->args; *d; d += 2)	    if (d[1] == 'D')	      break;	  /* Don't use for printout the variants of most floating	     point coprocessor instructions which use the same	     register number in two places, as above.  */	  if (*d == '\0')	    for (d = opc->args; *d; d += 2)	      if (d[1] == 't')		break;	  /* Don't match fmovel with more than one register;	     wait for fmoveml.  */	  if (*d == '\0')	    {	      for (d = opc->args; *d; d += 2)		{		  if (d[0] == 's' && d[1] == '8')		    {		      val = fetch_arg (buffer, d[1], 3, info);		      if ((val & (val - 1)) != 0)			break;		    }		}	    }	  if (*d == '\0')	    if ((val = match_insn_m68k (memaddr, info, opc, & priv)))	      return val;	}    }  /* Handle undefined instructions.  */  info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);  return 2;}/* **** End of m68k-dis.c *//* **** m68k-opc.h from sourceware.org CVS 2005-08-14.  *//* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,   2000, 2001, 2003, 2004, 2005   Free Software Foundation, Inc.   This file is part of GDB, GAS, and the GNU binutils.   GDB, GAS, and the GNU binutils are free software; you can redistribute   them and/or modify them under the terms of the GNU General Public   License as published by the Free Software Foundation; either version   1, or (at your option) any later version.   GDB, GAS, and the GNU binutils are distributed in the hope that they   will be useful, but WITHOUT ANY WARRANTY; without even the implied   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See   the GNU General Public License for more details.   You should have received a copy of the GNU General Public License   along with this file; see the file COPYING.  If not, write to the Free   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA   02110-1301, USA.  */#define one(x) ((unsigned int) (x) << 16)#define two(x, y) (((unsigned int) (x) << 16) + (y))/* The assembler requires that all instances of the same mnemonic must   be consecutive.  If they aren't, the assembler will bomb at   runtime.  */const struct m68k_opcode m68k_opcodes[] ={{"abcd", 2,	one(0140400),	one(0170770), "DsDd", m68000up },{"abcd", 2,	one(0140410),	one(0170770), "-s-d", m68000up },{"addaw", 2,	one(0150300),	one(0170700), "*wAd", m68000up },{"addal", 2,	one(0150700),	one(0170700), "*lAd", m68000up | mcfisa_a },{"addib", 4,	one(0003000),	one(0177700), "#b$s", m68000up },{"addiw", 4,	one(0003100),	one(0177700), "#w$s", m68000up },{"addil", 6,	one(0003200),	one(0177700), "#l$s", m68000up },{"addil", 6,	one(0003200),	one(0177700), "#lDs", mcfisa_a },{"addqb", 2,	one(0050000),	one(0170700), "Qd$b", m68000up },{"addqw", 2,	one(0050100),	one(0170700), "Qd%w", m68000up },{"addql", 2,	one(0050200),	one(0170700), "Qd%l", m68000up | mcfisa_a },/* The add opcode can generate the adda, addi, and addq instructions.  */{"addb", 2,	one(0050000),	one(0170700), "Qd$b", m68000up },{"addb", 4,	one(0003000),	one(0177700), "#b$s", m68000up },{"addb", 2,	one(0150000),	one(0170700), ";bDd", m68000up },{"addb", 2,	one(0150400),	one(0170700), "Dd~b", m68000up },{"addw", 2,	one(0050100),	one(0170700), "Qd%w", m68000up },{"addw", 2,	one(0150300),	one(0170700), "*wAd", m68000up },{"addw", 4,	one(0003100),	one(0177700), "#w$s", m68000up },{"addw", 2,	one(0150100),	one(0170700), "*wDd", m68000up },{"addw", 2,	one(0150500),	one(0170700), "Dd~w", m68000up },{"addl", 2,	one(0050200),	one(0170700), "Qd%l", m68000up | mcfisa_a },{"addl", 6,	one(0003200),	one(0177700), "#l$s", m68000up },{"addl", 6,	one(0003200),	one(0177700), "#lDs", mcfisa_a },{"addl", 2,	one(0150700),	one(0170700), "*lAd", m68000up | mcfisa_a },{"addl", 2,	one(0150200),	one(0170700), "*lDd", m68000up | mcfisa_a },{"addl", 2,	one(0150600),	one(0170700), "Dd~l", m68000up | mcfisa_a },{"addxb", 2,	one(0150400),	one(0170770), "DsDd", m68000up },{"addxb", 2,	one(0150410),	one(0170770), "-s-d", m68000up },{"addxw", 2,	one(0150500),	one(0170770), "DsDd", m68000up },{"addxw", 2,	one(0150510),	one(0170770), "-s-d", m68000up },{"addxl", 2,	one(0150600),	one(0170770), "DsDd", m68000up | mcfisa_a },{"addxl", 2,	one(0150610),	one(0170770), "-s-d", m68000up },{"andib", 4,	one(0001000),	one(0177700), "#b$s", m68000up },{"andib", 4,	one(0001074),	one(0177777), "#bCs", m68000up },{"andiw", 4,	one(0001100),	one(0177700), "#w$s", m68000up },{"andiw", 4,	one(0001174),	one(0177777), "#wSs", m68000up },{"andil", 6,	one(0001200),	one(0177700), "#l$s", m68000up },{"andil", 6,	one(0001200),	one(0177700), "#lDs", mcfisa_a },{"andi", 4,	one(0001100),	one(0177700), "#w$s", m68000up },{"andi", 4,	one(0001074),	one(0177777), "#bCs", m68000up },{"andi", 4,	one(0001174),	one(0177777), "#wSs", m68000up },/* The and opcode can generate the andi instruction.  */{"andb", 4,	one(0001000),	one(0177700), "#b$s", m68000up },{"andb", 4,	one(0001074),	one(0177777), "#bCs", m68000up },{"andb", 2,	one(0140000),	one(0170700), ";bDd", m68000up },{"andb", 2,	one(0140400),	one(0170700), "Dd~b", m68000up },{"andw", 4,	one(0001100),	one(0177700), "#w$s", m68000up },{"andw", 4,	one(0001174),	one(0177777), "#wSs", m68000up },{"andw", 2,	one(0140100),	one(0170700), ";wDd", m68000up },{"andw", 2,	one(0140500),	one(0170700), "Dd~w", m68000up },{"andl", 6,	one(0001200),	one(0177700), "#l$s", m68000up },{"andl", 6,	one(0001200),	one(0177700), "#lDs", mcfisa_a },{"andl", 2,	one(0140200),	one(0170700), ";lDd", m68000up | mcfisa_a },{"andl", 2,	one(0140600),	one(0170700), "Dd~l", m68000up | mcfisa_a },{"and", 4,	one(0001100),	one(0177700), "#w$w", m68000up },{"and", 4,	one(0001074),	one(0177777), "#bCs", m68000up },{"and", 4,	one(0001174),	one(0177777), "#wSs", m68000up },{"and", 2,	one(0140100),	one(0170700), ";wDd", m68000up },{"and", 2,	one(0140500),	one(0170700), "Dd~w", m68000up },{"aslb", 2,	one(0160400),	one(0170770), "QdDs", m68000up },{"aslb", 2,	one(0160440),	one(0170770), "DdDs", m68000up },{"aslw", 2,	one(0160500),	one(0170770), "QdDs", m68000up },{"aslw", 2,	one(0160540),	one(0170770), "DdDs", m68000up },{"aslw", 2,	one(0160700),	one(0177700), "~s",   m68000up },{"asll", 2,	one(0160600),	one(0170770), "QdDs", m68000up | mcfisa_a },{"asll", 2,	one(0160640),	one(0170770), "DdDs", m68000up | mcfisa_a },{"asrb", 2,	one(0160000),	one(0170770), "QdDs", m68000up },{"asrb", 2,	one(0160040),	one(0170770), "DdDs", m68000up },{"asrw", 2,	one(0160100),	one(0170770), "QdDs", m68000up },{"asrw", 2,	one(0160140),	one(0170770), "DdDs", m68000up },{"asrw", 2,	one(0160300),	one(0177700), "~s",   m68000up },{"asrl", 2,	one(0160200),	one(0170770), "QdDs", m68000up | mcfisa_a },{"asrl", 2,	one(0160240),	one(0170770), "DdDs", m68000up | mcfisa_a },{"bhiw", 2,	one(0061000),	one(0177777), "BW", m68000up | mcfisa_a },{"blsw", 2,	one(0061400),	one(0177777), "BW", m68000up | mcfisa_a },{"bccw", 2,	one(0062000),	one(0177777), "BW", m68000up | mcfisa_a },{"bcsw", 2,	one(0062400),	one(0177777), "BW", m68000up | mcfisa_a },{"bnew", 2,	one(0063000),	one(0177777), "BW", m68000up | mcfisa_a },{"beqw", 2,	one(0063400),	one(0177777), "BW", m68000up | mcfisa_a },{"bvcw", 2,	one(0064000),	one(0177777), "BW", m68000up | mcfisa_a },{"bvsw", 2,	one(0064400),	one(0177777), "BW", m68000up | mcfisa_a },{"bplw", 2,	one(0065000),	one(0177777), "BW", m68000up | mcfisa_a },{"bmiw", 2,	one(0065400),	one(0177777), "BW", m68000up | mcfisa_a },{"bgew", 2,	one(0066000),	one(0177777), "BW", m68000up | mcfisa_a },{"bltw", 2,	one(0066400),	one(0177777), "BW", m68000up | mcfisa_a },{"bgtw", 2,	one(0067000),	one(0177777), "BW", m68000up | mcfisa_a },{"blew", 2,	one(0067400),	one(0177777), "BW", m68000up | mcfisa_a },{"bhil", 2,	one(0061377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"blsl", 2,	one(0061777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bccl", 2,	one(0062377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bcsl", 2,	one(0062777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bnel", 2,	one(0063377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"beql", 2,	one(0063777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bvcl", 2,	one(0064377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bvsl", 2,	one(0064777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bpll", 2,	one(0065377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bmil", 2,	one(0065777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bgel", 2,	one(0066377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bltl", 2,	one(0066777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bgtl", 2,	one(0067377),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"blel", 2,	one(0067777),	one(0177777), "BL", m68020up | cpu32 | mcfisa_b},{"bhis", 2,	one(0061000),	one(0177400), "BB", m68000up | mcfisa_a },{"blss", 2,	one(0061400),	one(0177400), "BB", m68000up | mcfisa_a },{"bccs", 2,	one(0062000),	one(0177400), "BB", m68000up | mcfisa_a },{"bcss", 2,	one(0062400),	one(0177400), "BB", m68000up | mcfisa_a },{"bnes", 2,	one(0063000),	one(0177400), "BB", m68000up | mcfisa_a },{"beqs", 2,	one(0063400),	one(0177400), "BB", m68000up | mcfisa_a },{"bvcs", 2,	one(0064000),	one(0177400), "BB", m68000up | mcfisa_a },{"bvss", 2,	one(0064