/* *  MIPS emulation for qemu: CPU initialisation routines. * *  Copyright (c) 2004-2005 Jocelyn Mayer *  Copyright (c) 2007 Herve Poussineau * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA *//* CPU / CPU family specific config register values. *//* Have config1, uncached coherency */#define MIPS_CONFIG0                                              \  ((1 << CP0C0_M) | (0x2 << CP0C0_K0))/* Have config2, no coprocessor2 attached, no MDMX support attached,   no performance counters, watch registers present,   no code compression, EJTAG present, no FPU */#define MIPS_CONFIG1                                              \((1 << CP0C1_M) |                                                 \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \ (0 << CP0C1_FP))/* Have config3, no tertiary/secondary caches implemented */#define MIPS_CONFIG2                                              \((1 << CP0C2_M))/* No config4, no DSP ASE, no large physaddr (PABITS),   no external interrupt controller, no vectored interupts,   no 1kb pages, no SmartMIPS ASE, no trace logic */#define MIPS_CONFIG3                                              \((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \ (0 << CP0C3_SM) | (0 << CP0C3_TL))/* Define a implementation number of 1.   Define a major version 1, minor version 0. */#define MIPS_FCR0 ((0 << FCR0_S) | (0x1 << FCR0_PRID) | (0x10 << FCR0_REV))/* MMU types, the first four entries have the same layout as the   CP0C0_MT field.  */enum mips_mmu_types {    MMU_TYPE_NONE,    MMU_TYPE_R4000,    MMU_TYPE_RESERVED,    MMU_TYPE_FMT,    MMU_TYPE_R3000,    MMU_TYPE_R6000,    MMU_TYPE_R8000};struct mips_def_t {    const unsigned char *name;    int32_t CP0_PRid;    int32_t CP0_Config0;    int32_t CP0_Config1;    int32_t CP0_Config2;    int32_t CP0_Config3;    int32_t CP0_Config6;    int32_t CP0_Config7;    int32_t SYNCI_Step;    int32_t CCRes;    int32_t CP0_Status_rw_bitmask;    int32_t CP0_TCStatus_rw_bitmask;    int32_t CP0_SRSCtl;    int32_t CP1_fcr0;    int32_t SEGBITS;    int32_t PABITS;    int32_t CP0_SRSConf0_rw_bitmask;    int32_t CP0_SRSConf0;    int32_t CP0_SRSConf1_rw_bitmask;    int32_t CP0_SRSConf1;    int32_t CP0_SRSConf2_rw_bitmask;    int32_t CP0_SRSConf2;    int32_t CP0_SRSConf3_rw_bitmask;    int32_t CP0_SRSConf3;    int32_t CP0_SRSConf4_rw_bitmask;    int32_t CP0_SRSConf4;    int insn_flags;    enum mips_mmu_types mmu_type;};/*****************************************************************************//* MIPS CPU definitions */static mips_def_t mips_defs[] ={    {        .name = "4Kc",        .CP0_PRid = 0x00018000,        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3,        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1278FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32 | ASE_MIPS16,        .mmu_type = MMU_TYPE_R4000,    },    {        .name = "4Km",        .CP0_PRid = 0x00018300,        /* Config1 implemented, fixed mapping MMU,           no virtual icache, uncached coherency. */        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3,        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1258FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32 | ASE_MIPS16,        .mmu_type = MMU_TYPE_FMT,    },    {        .name = "4KEcR1",        .CP0_PRid = 0x00018400,        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3,        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1278FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32 | ASE_MIPS16,        .mmu_type = MMU_TYPE_R4000,    },    {        .name = "4KEmR1",        .CP0_PRid = 0x00018500,        .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3,        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1258FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32 | ASE_MIPS16,        .mmu_type = MMU_TYPE_FMT,    },    {        .name = "4KEc",        .CP0_PRid = 0x00019000,        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |                    (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1278FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,        .mmu_type = MMU_TYPE_R4000,    },    {        .name = "4KEm",        .CP0_PRid = 0x00019100,        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |                    (MMU_TYPE_FMT << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3,        .SYNCI_Step = 32,        .CCRes = 2,        .CP0_Status_rw_bitmask = 0x1258FF17,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,        .mmu_type = MMU_TYPE_FMT,    },    {        .name = "24Kc",        .CP0_PRid = 0x00019300,        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |                    (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),        .SYNCI_Step = 32,        .CCRes = 2,        /* No DSP implemented. */        .CP0_Status_rw_bitmask = 0x1278FF1F,        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,        .mmu_type = MMU_TYPE_R4000,    },    {        .name = "24Kf",        .CP0_PRid = 0x00019300,        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |                    (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),        .SYNCI_Step = 32,        .CCRes = 2,        /* No DSP implemented. */        .CP0_Status_rw_bitmask = 0x3678FF1F,        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |                    (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,        .mmu_type = MMU_TYPE_R4000,    },    {        .name = "34Kf",        .CP0_PRid = 0x00019500,        .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |                    (MMU_TYPE_R4000 << CP0C0_MT),        .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |		    (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |		    (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),        .CP0_Config2 = MIPS_CONFIG2,        .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_MT),        .SYNCI_Step = 32,        .CCRes = 2,        /* No DSP implemented. */        .CP0_Status_rw_bitmask = 0x3678FF1F,        /* No DSP implemented. */        .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |                    (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |                    (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |                    (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |                    (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |                    (0xff << CP0TCSt_TASID),        .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |                    (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),        .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),        .CP0_SRSConf0_rw_bitmask = 0x3fffffff,        .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |                    (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),        .CP0_SRSConf1_rw_bitmask = 0x3fffffff,        .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |                    (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),        .CP0_SRSConf2_rw_bitmask = 0x3fffffff,        .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |                    (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),        .CP0_SRSConf3_rw_bitmask = 0x3fffffff,        .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |                    (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),        .CP0_SRSConf4_rw_bitmask = 0x3fffffff,        .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |                    (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),        .SEGBITS = 32,        .PABITS = 32,        .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,        .mmu_type = MMU_TYPE_R4000,