/* *  MIPS emulation helpers for qemu. * *  Copyright (c) 2004-2005 Jocelyn Mayer * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA */#include <stdarg.h>#include <stdlib.h>#include <stdio.h>#include <string.h>#include <inttypes.h>#include <signal.h>#include <assert.h>#include "cpu.h"#include "exec-all.h"enum {    TLBRET_DIRTY = -4,    TLBRET_INVALID = -3,    TLBRET_NOMATCH = -2,    TLBRET_BADADDR = -1,    TLBRET_MATCH = 0};/* no MMU emulation */int no_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,                        target_ulong address, int rw, int access_type){    *physical = address;    *prot = PAGE_READ | PAGE_WRITE;    return TLBRET_MATCH;}/* fixed mapping MMU emulation */int fixed_mmu_map_address (CPUState *env, target_ulong *physical, int *prot,                           target_ulong address, int rw, int access_type){    if (address <= (int32_t)0x7FFFFFFFUL) {        if (!(env->CP0_Status & (1 << CP0St_ERL)))            *physical = address + 0x40000000UL;        else            *physical = address;    } else if (address <= (int32_t)0xBFFFFFFFUL)        *physical = address & 0x1FFFFFFF;    else        *physical = address;    *prot = PAGE_READ | PAGE_WRITE;    return TLBRET_MATCH;}/* MIPS32/MIPS64 R4000-style MMU emulation */int r4k_map_address (CPUState *env, target_ulong *physical, int *prot,                     target_ulong address, int rw, int access_type){    uint8_t ASID = env->CP0_EntryHi & 0xFF;    int i;    for (i = 0; i < env->tlb->tlb_in_use; i++) {        r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];        /* 1k pages are not supported. */        target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);        target_ulong tag = address & ~mask;        target_ulong VPN = tlb->VPN & ~mask;#if defined(TARGET_MIPS64)        tag &= env->SEGMask;#endif        /* Check ASID, virtual page number & size */        if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {            /* TLB match */            int n = !!(address & mask & ~(mask >> 1));            /* Check access rights */            if (!(n ? tlb->V1 : tlb->V0))                return TLBRET_INVALID;            if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {                *physical = tlb->PFN[n] | (address & (mask >> 1));                *prot = PAGE_READ;                if (n ? tlb->D1 : tlb->D0)                    *prot |= PAGE_WRITE;                return TLBRET_MATCH;            }            return TLBRET_DIRTY;        }    }    return TLBRET_NOMATCH;}static int get_physical_address (CPUState *env, target_ulong *physical,                                int *prot, target_ulong address,                                int rw, int access_type){    /* User mode can only access useg/xuseg */    int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;    int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;    int kernel_mode = !user_mode && !supervisor_mode;#if defined(TARGET_MIPS64)    int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;    int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;    int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;#endif    int ret = TLBRET_MATCH;#if 0    if (logfile) {        fprintf(logfile, "user mode %d h %08x\n",                user_mode, env->hflags);    }#endif    if (address <= (int32_t)0x7FFFFFFFUL) {        /* useg */        if (env->CP0_Status & (1 << CP0St_ERL)) {            *physical = address & 0xFFFFFFFF;            *prot = PAGE_READ | PAGE_WRITE;        } else {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);        }#if defined(TARGET_MIPS64)    } else if (address < 0x4000000000000000ULL) {        /* xuseg */	if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);	} else {	    ret = TLBRET_BADADDR;        }    } else if (address < 0x8000000000000000ULL) {        /* xsseg */	if ((supervisor_mode || kernel_mode) &&	    SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);	} else {	    ret = TLBRET_BADADDR;        }    } else if (address < 0xC000000000000000ULL) {        /* xkphys */        if (kernel_mode && KX &&            (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {            *physical = address & env->PAMask;            *prot = PAGE_READ | PAGE_WRITE;	} else {	    ret = TLBRET_BADADDR;	}    } else if (address < 0xFFFFFFFF80000000ULL) {        /* xkseg */	if (kernel_mode && KX &&	    address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);	} else {	    ret = TLBRET_BADADDR;	}#endif    } else if (address < (int32_t)0xA0000000UL) {        /* kseg0 */        if (kernel_mode) {            *physical = address - (int32_t)0x80000000UL;            *prot = PAGE_READ | PAGE_WRITE;        } else {            ret = TLBRET_BADADDR;        }    } else if (address < (int32_t)0xC0000000UL) {        /* kseg1 */        if (kernel_mode) {            *physical = address - (int32_t)0xA0000000UL;            *prot = PAGE_READ | PAGE_WRITE;        } else {            ret = TLBRET_BADADDR;        }    } else if (address < (int32_t)0xE0000000UL) {        /* sseg (kseg2) */        if (supervisor_mode || kernel_mode) {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);        } else {            ret = TLBRET_BADADDR;        }    } else {        /* kseg3 */        /* XXX: debug segment is not emulated */        if (kernel_mode) {            ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);        } else {            ret = TLBRET_BADADDR;        }    }#if 0    if (logfile) {        fprintf(logfile, TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",		address, rw, access_type, *physical, *prot, ret);    }#endif    return ret;}#if defined(CONFIG_USER_ONLY)target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr){    return addr;}#elsetarget_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr){    target_ulong phys_addr;    int prot;    if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)        return -1;    return phys_addr;}void cpu_mips_init_mmu (CPUState *env){}#endif /* !defined(CONFIG_USER_ONLY) */int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,                               int mmu_idx, int is_softmmu){    target_ulong physical;    int prot;    int exception = 0, error_code = 0;    int access_type;    int ret = 0;    if (logfile) {#if 0        cpu_dump_state(env, logfile, fprintf, 0);#endif        fprintf(logfile, "%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",                __func__, env->PC[env->current_tc], address, rw, mmu_idx, is_softmmu);    }    rw &= 1;    /* data access */    /* XXX: put correct access by using cpu_restore_state()       correctly */    access_type = ACCESS_INT;    if (env->user_mode_only) {        /* user mode only emulation */        ret = TLBRET_NOMATCH;        goto do_fault;    }    ret = get_physical_address(env, &physical, &prot,                               address, rw, access_type);    if (logfile) {        fprintf(logfile, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_lx " prot %d\n",                __func__, address, ret, physical, prot);    }    if (ret == TLBRET_MATCH) {       ret = tlb_set_page(env, address & TARGET_PAGE_MASK,                          physical & TARGET_PAGE_MASK, prot,                          mmu_idx, is_softmmu);    } else if (ret < 0) {    do_fault:        switch (ret) {        default:        case TLBRET_BADADDR:            /* Reference to kernel address from user mode or supervisor mode */            /* Reference to supervisor address from user mode */            if (rw)                exception = EXCP_AdES;            else                exception = EXCP_AdEL;            break;        case TLBRET_NOMATCH:            /* No TLB match for a mapped address */            if (rw)                exception = EXCP_TLBS;            else                exception = EXCP_TLBL;            error_code = 1;            break;        case TLBRET_INVALID:            /* TLB match with no valid bit */            if (rw)                exception = EXCP_TLBS;            else                exception = EXCP_TLBL;            break;        case TLBRET_DIRTY:            /* TLB match but 'D' bit is cleared */            exception = EXCP_LTLBL;            break;        }        /* Raise exception */        env->CP0_BadVAddr = address;        env->CP0_Context = (env->CP0_Context & ~0x007fffff) |	                   ((address >> 9) &   0x007ffff0);        env->CP0_EntryHi =            (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));#if defined(TARGET_MIPS64)        env->CP0_EntryHi &= env->SEGMask;        env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |                            ((address & 0xC00000000000ULL) >> (env->SEGBITS - 9)) |                            ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);#endif        env->exception_index = exception;        env->error_code = error_code;        ret = 1;    }    return ret;}