/* Print i386 instructions for GDB, the GNU debugger.   Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,   2001   Free Software Foundation, Inc.This file is part of GDB.This program is free software; you can redistribute it and/or modifyit under the terms of the GNU General Public License as published bythe Free Software Foundation; either version 2 of the License, or(at your option) any later version.This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; without even the implied warranty ofMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See theGNU General Public License for more details.You should have received a copy of the GNU General Public Licensealong with this program; if not, write to the Free SoftwareFoundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *//* * 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) * July 1988 *  modified by John Hassey (hassey@dg-rtp.dg.com) *  x86-64 support added by Jan Hubicka (jh@suse.cz) *//* * The main tables describing the instructions is essentially a copy * of the "Opcode Map" chapter (Appendix A) of the Intel 80386 * Programmers Manual.  Usually, there is a capital letter, followed * by a small letter.  The capital letter tell the addressing mode, * and the small letter tells about the operand size.  Refer to * the Intel manual for details. */#include <stdlib.h>#include "dis-asm.h"#define MAXLEN 20#include <setjmp.h>#ifndef UNIXWARE_COMPAT/* Set non-zero for broken, compatible instructions.  Set to zero for   non-broken opcodes.  */#define UNIXWARE_COMPAT 1#endifstatic int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *));static void ckprefix PARAMS ((void));static const char *prefix_name PARAMS ((int, int));static int print_insn PARAMS ((bfd_vma, disassemble_info *));static void dofloat PARAMS ((int));static void OP_ST PARAMS ((int, int));static void OP_STi  PARAMS ((int, int));static int putop PARAMS ((const char *, int));static void oappend PARAMS ((const char *));static void append_seg PARAMS ((void));static void OP_indirE PARAMS ((int, int));static void print_operand_value PARAMS ((char *, int, bfd_vma));static void OP_E PARAMS ((int, int));static void OP_G PARAMS ((int, int));static bfd_vma get64 PARAMS ((void));static bfd_signed_vma get32 PARAMS ((void));static bfd_signed_vma get32s PARAMS ((void));static int get16 PARAMS ((void));static void set_op PARAMS ((bfd_vma, int));static void OP_REG PARAMS ((int, int));static void OP_IMREG PARAMS ((int, int));static void OP_I PARAMS ((int, int));static void OP_I64 PARAMS ((int, int));static void OP_sI PARAMS ((int, int));static void OP_J PARAMS ((int, int));static void OP_SEG PARAMS ((int, int));static void OP_DIR PARAMS ((int, int));static void OP_OFF PARAMS ((int, int));static void OP_OFF64 PARAMS ((int, int));static void ptr_reg PARAMS ((int, int));static void OP_ESreg PARAMS ((int, int));static void OP_DSreg PARAMS ((int, int));static void OP_C PARAMS ((int, int));static void OP_D PARAMS ((int, int));static void OP_T PARAMS ((int, int));static void OP_Rd PARAMS ((int, int));static void OP_MMX PARAMS ((int, int));static void OP_XMM PARAMS ((int, int));static void OP_EM PARAMS ((int, int));static void OP_EX PARAMS ((int, int));static void OP_MS PARAMS ((int, int));static void OP_XS PARAMS ((int, int));static void OP_3DNowSuffix PARAMS ((int, int));static void OP_SIMD_Suffix PARAMS ((int, int));static void SIMD_Fixup PARAMS ((int, int));static void BadOp PARAMS ((void));struct dis_private {  /* Points to first byte not fetched.  */  bfd_byte *max_fetched;  bfd_byte the_buffer[MAXLEN];  bfd_vma insn_start;  int orig_sizeflag;  jmp_buf bailout;};/* The opcode for the fwait instruction, which we treat as a prefix   when we can.  */#define FWAIT_OPCODE (0x9b)/* Set to 1 for 64bit mode disassembly.  */static int mode_64bit;/* Flags for the prefixes for the current instruction.  See below.  */static int prefixes;/* REX prefix the current instruction.  See below.  */static int rex;/* Bits of REX we've already used.  */static int rex_used;#define REX_MODE64	8#define REX_EXTX	4#define REX_EXTY	2#define REX_EXTZ	1/* Mark parts used in the REX prefix.  When we are testing for   empty prefix (for 8bit register REX extension), just mask it   out.  Otherwise test for REX bit is excuse for existence of REX   only in case value is nonzero.  */#define USED_REX(value)					\  {							\    if (value)						\      rex_used |= (rex & value) ? (value) | 0x40 : 0;	\    else						\      rex_used |= 0x40;					\  }/* Flags for prefixes which we somehow handled when printing the   current instruction.  */static int used_prefixes;/* Flags stored in PREFIXES.  */#define PREFIX_REPZ 1#define PREFIX_REPNZ 2#define PREFIX_LOCK 4#define PREFIX_CS 8#define PREFIX_SS 0x10#define PREFIX_DS 0x20#define PREFIX_ES 0x40#define PREFIX_FS 0x80#define PREFIX_GS 0x100#define PREFIX_DATA 0x200#define PREFIX_ADDR 0x400#define PREFIX_FWAIT 0x800/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)   to ADDR (exclusive) are valid.  Returns 1 for success, longjmps   on error.  */#define FETCH_DATA(info, addr) \  ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \   ? 1 : fetch_data ((info), (addr)))static intfetch_data (info, addr)     struct disassemble_info *info;     bfd_byte *addr;{  int status;  struct dis_private *priv = (struct dis_private *) info->private_data;  bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer);  status = (*info->read_memory_func) (start,				      priv->max_fetched,				      addr - priv->max_fetched,				      info);  if (status != 0)    {      /* If we did manage to read at least one byte, then         print_insn_i386 will do something sensible.  Otherwise, print         an error.  We do that here because this is where we know         STATUS.  */      if (priv->max_fetched == priv->the_buffer)	(*info->memory_error_func) (status, start, info);      longjmp (priv->bailout, 1);    }  else    priv->max_fetched = addr;  return 1;}#define XX NULL, 0#define Eb OP_E, b_mode#define Ev OP_E, v_mode#define Ed OP_E, d_mode#define indirEb OP_indirE, b_mode#define indirEv OP_indirE, v_mode#define Ew OP_E, w_mode#define Ma OP_E, v_mode#define M OP_E, 0		/* lea, lgdt, etc. */#define Mp OP_E, 0		/* 32 or 48 bit memory operand for LDS, LES etc */#define Gb OP_G, b_mode#define Gv OP_G, v_mode#define Gd OP_G, d_mode#define Gw OP_G, w_mode#define Rd OP_Rd, d_mode#define Rm OP_Rd, m_mode#define Ib OP_I, b_mode#define sIb OP_sI, b_mode	/* sign extened byte */#define Iv OP_I, v_mode#define Iq OP_I, q_mode#define Iv64 OP_I64, v_mode#define Iw OP_I, w_mode#define Jb OP_J, b_mode#define Jv OP_J, v_mode#define Cm OP_C, m_mode#define Dm OP_D, m_mode#define Td OP_T, d_mode#define RMeAX OP_REG, eAX_reg#define RMeBX OP_REG, eBX_reg#define RMeCX OP_REG, eCX_reg#define RMeDX OP_REG, eDX_reg#define RMeSP OP_REG, eSP_reg#define RMeBP OP_REG, eBP_reg#define RMeSI OP_REG, eSI_reg#define RMeDI OP_REG, eDI_reg#define RMrAX OP_REG, rAX_reg#define RMrBX OP_REG, rBX_reg#define RMrCX OP_REG, rCX_reg#define RMrDX OP_REG, rDX_reg#define RMrSP OP_REG, rSP_reg#define RMrBP OP_REG, rBP_reg#define RMrSI OP_REG, rSI_reg#define RMrDI OP_REG, rDI_reg#define RMAL OP_REG, al_reg#define RMAL OP_REG, al_reg#define RMCL OP_REG, cl_reg#define RMDL OP_REG, dl_reg#define RMBL OP_REG, bl_reg#define RMAH OP_REG, ah_reg#define RMCH OP_REG, ch_reg#define RMDH OP_REG, dh_reg#define RMBH OP_REG, bh_reg#define RMAX OP_REG, ax_reg#define RMDX OP_REG, dx_reg#define eAX OP_IMREG, eAX_reg#define eBX OP_IMREG, eBX_reg#define eCX OP_IMREG, eCX_reg#define eDX OP_IMREG, eDX_reg#define eSP OP_IMREG, eSP_reg#define eBP OP_IMREG, eBP_reg#define eSI OP_IMREG, eSI_reg#define eDI OP_IMREG, eDI_reg#define AL OP_IMREG, al_reg#define AL OP_IMREG, al_reg#define CL OP_IMREG, cl_reg#define DL OP_IMREG, dl_reg#define BL OP_IMREG, bl_reg#define AH OP_IMREG, ah_reg#define CH OP_IMREG, ch_reg#define DH OP_IMREG, dh_reg#define BH OP_IMREG, bh_reg#define AX OP_IMREG, ax_reg#define DX OP_IMREG, dx_reg#define indirDX OP_IMREG, indir_dx_reg#define Sw OP_SEG, w_mode#define Ap OP_DIR, 0#define Ob OP_OFF, b_mode#define Ob64 OP_OFF64, b_mode#define Ov OP_OFF, v_mode#define Ov64 OP_OFF64, v_mode#define Xb OP_DSreg, eSI_reg#define Xv OP_DSreg, eSI_reg#define Yb OP_ESreg, eDI_reg#define Yv OP_ESreg, eDI_reg#define DSBX OP_DSreg, eBX_reg#define es OP_REG, es_reg#define ss OP_REG, ss_reg#define cs OP_REG, cs_reg#define ds OP_REG, ds_reg#define fs OP_REG, fs_reg#define gs OP_REG, gs_reg#define MX OP_MMX, 0#define XM OP_XMM, 0#define EM OP_EM, v_mode#define EX OP_EX, v_mode#define MS OP_MS, v_mode#define XS OP_XS, v_mode#define None OP_E, 0#define OPSUF OP_3DNowSuffix, 0#define OPSIMD OP_SIMD_Suffix, 0#define cond_jump_flag NULL, cond_jump_mode#define loop_jcxz_flag NULL, loop_jcxz_mode/* bits in sizeflag */#define SUFFIX_ALWAYS 4#define AFLAG 2#define DFLAG 1#define b_mode 1  /* byte operand */#define v_mode 2  /* operand size depends on prefixes */#define w_mode 3  /* word operand */#define d_mode 4  /* double word operand  */#define q_mode 5  /* quad word operand */#define x_mode 6#define m_mode 7  /* d_mode in 32bit, q_mode in 64bit mode.  */#define cond_jump_mode 8#define loop_jcxz_mode 9#define es_reg 100#define cs_reg 101#define ss_reg 102#define ds_reg 103#define fs_reg 104#define gs_reg 105#define eAX_reg 108#define eCX_reg 109#define eDX_reg 110#define eBX_reg 111#define eSP_reg 112#define eBP_reg 113#define eSI_reg 114#define eDI_reg 115#define al_reg 116#define cl_reg 117#define dl_reg 118#define bl_reg 119#define ah_reg 120#define ch_reg 121#define dh_reg 122#define bh_reg 123#define ax_reg 124#define cx_reg 125#define dx_reg 126#define bx_reg 127#define sp_reg 128#define bp_reg 129#define si_reg 130#define di_reg 131#define rAX_reg 132#define rCX_reg 133#define rDX_reg 134#define rBX_reg 135#define rSP_reg 136#define rBP_reg 137#define rSI_reg 138#define rDI_reg 139#define indir_dx_reg 150#define FLOATCODE 1#define USE_GROUPS 2#define USE_PREFIX_USER_TABLE 3#define X86_64_SPECIAL 4#define FLOAT	  NULL, NULL, FLOATCODE, NULL, 0, NULL, 0#define GRP1b	  NULL, NULL, USE_GROUPS, NULL,  0, NULL, 0#define GRP1S	  NULL, NULL, USE_GROUPS, NULL,  1, NULL, 0#define GRP1Ss	  NULL, NULL, USE_GROUPS, NULL,  2, NULL, 0#define GRP2b	  NULL, NULL, USE_GROUPS, NULL,  3, NULL, 0#define GRP2S	  NULL, NULL, USE_GROUPS, NULL,  4, NULL, 0#define GRP2b_one NULL, NULL, USE_GROUPS, NULL,  5, NULL, 0#define GRP2S_one NULL, NULL, USE_GROUPS, NULL,  6, NULL, 0#define GRP2b_cl  NULL, NULL, USE_GROUPS, NULL,  7, NULL, 0#define GRP2S_cl  NULL, NULL, USE_GROUPS, NULL,  8, NULL, 0#define GRP3b	  NULL, NULL, USE_GROUPS, NULL,  9, NULL, 0#define GRP3S	  NULL, NULL, USE_GROUPS, NULL, 10, NULL, 0#define GRP4	  NULL, NULL, USE_GROUPS, NULL, 11, NULL, 0#define GRP5	  NULL, NULL, USE_GROUPS, NULL, 12, NULL, 0#define GRP6	  NULL, NULL, USE_GROUPS, NULL, 13, NULL, 0#define GRP7	  NULL, NULL, USE_GROUPS, NULL, 14, NULL, 0#define GRP8	  NULL, NULL, USE_GROUPS, NULL, 15, NULL, 0#define GRP9	  NULL, NULL, USE_GROUPS, NULL, 16, NULL, 0#define GRP10	  NULL, NULL, USE_GROUPS, NULL, 17, NULL, 0#define GRP11	  NULL, NULL, USE_GROUPS, NULL, 18, NULL, 0#define GRP12	  NULL, NULL, USE_GROUPS, NULL, 19, NULL, 0#define GRP13	  NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0#define GRP14	  NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0#define GRPAMD	  NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0#define PREGRP0   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  0, NULL, 0#define PREGRP1   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  1, NULL, 0#define PREGRP2   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  2, NULL, 0#define PREGRP3   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  3, NULL, 0#define PREGRP4   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  4, NULL, 0#define PREGRP5   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  5, NULL, 0#define PREGRP6   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  6, NULL, 0#define PREGRP7   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  7, NULL, 0#define PREGRP8   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  8, NULL, 0#define PREGRP9   NULL, NULL, USE_PREFIX_USER_TABLE, NULL,  9, NULL, 0#define PREGRP10  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 10, NULL, 0#define PREGRP11  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 11, NULL, 0#define PREGRP12  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 12, NULL, 0#define PREGRP13  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 13, NULL, 0#define PREGRP14  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 14, NULL, 0#define PREGRP15  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 15, NULL, 0#define PREGRP16  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 16, NULL, 0#define PREGRP17  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 17, NULL, 0#define PREGRP18  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 18, NULL, 0#define PREGRP19  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 19, NULL, 0#define PREGRP20  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 20, NULL, 0#define PREGRP21  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 21, NULL, 0#define PREGRP22  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 22, NULL, 0#define PREGRP23  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 23, NULL, 0#define PREGRP24  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0#define PREGRP25  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0#define PREGRP26  NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0#define X86_64_0  NULL, NULL, X86_64_SPECIAL, NULL,  0, NULL, 0typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag));struct dis386 {  const char *name;  op_rtn op1;  int bytemode1;  op_rtn op2;  int bytemode2;  op_rtn op3;  int bytemode3;};/* Upper case letters in the instruction names here are macros.   'A' => print 'b' if no register operands or suffix_always is true   'B' => print 'b' if suffix_always is true   'E' => print 'e' if 32-bit form of jcxz   'F' => print 'w' or 'l' depending on address size prefix (loop insns)   'H' => print ",pt" or ",pn" branch hint   'L' => print 'l' if suffix_always is true   'N' => print 'n' if instruction has no wait "prefix"   'O' => print 'd', or 'o'   'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,   .      or suffix_always is true.  print 'q' if rex prefix is present.   'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always   .      is true   'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode)   'S' => print 'w', 'l' or 'q' if suffix_always is true   'T' => print 'q' in 64bit mode and behave as 'P' otherwise   'U' => print 'q' in 64bit mode and behave as 'Q' otherwise   'X' => print 's', 'd' depending on data16 prefix (for XMM)   'W' => print 'b' or 'w' ("w" or "de" in intel mode)   'Y' => 'q' if instruction has an REX 64bit overwrite prefix   Many of the above letters print nothing in Intel mode.  See "putop"   for the details.   Braces '{' and '}', and vertical bars '|', indicate alternative   mnemonic strings for AT&T, Intel, X86_64 AT&T, and X86_64 Intel   modes.  In cases where there are only two alternatives, the X86_64   instruction is reserved, and "(bad)" is printed.*/static const struct dis386 dis386[] = {  /* 00 */  { "addB",		Eb, Gb, XX },  { "addS",		Ev, Gv, XX },  { "addB",		Gb, Eb, XX },  { "addS",		Gv, Ev, XX },  { "addB",		AL, Ib, XX },  { "addS",		eAX, Iv, XX },  { "push{T|}",		es, XX, XX },  { "pop{T|}",		es, XX, XX },  /* 08 */  { "orB",		Eb, Gb, XX },  { "orS",		Ev, Gv, XX },  { "orB",		Gb, Eb, XX },  { "orS",		Gv, Ev, XX },  { "orB",		AL, Ib, XX },  { "orS",		eAX, Iv, XX },  { "push{T|}",		cs, XX, XX },  { "(bad)",		XX, XX, XX },	/* 0x0f extended opcode escape */  /* 10 */  { "adcB",		Eb, Gb, XX },  { "adcS",		Ev, Gv, XX },  { "adcB",		Gb, Eb, XX },  { "adcS",		Gv, Ev, XX },  { "adcB",		AL, Ib, XX },  { "adcS",		eAX, Iv, XX },  { "push{T|}",		ss, XX, XX },  { "popT|}",		ss, XX, XX },  /* 18 */  { "sbbB",		Eb, Gb, XX },  { "sbbS",		Ev, Gv, XX },  { "sbbB",		Gb, Eb, XX },  { "sbbS",		Gv, Ev, XX },