+	}+	else+	  {+	    outportb(ISR, 0xfe);	+	  }+	+	spin_unlock(&priv->lock);+}+++/*+ * Open and Close+ */+static int nic_8019_open(struct net_device *dev)+{+	int i;++	MOD_INC_USE_COUNT;+	TRACE("open\n");+	// Disable irqs+	disable_irq(dev->irq);+	// register rx isr+	if(request_irq(dev->irq, &nic_8019_rx, SA_INTERRUPT, "eth rx isr", dev)) {+	  printk(KERN_ERR "Rtl8019: Can't get irq %d\n", dev->irq);+	  return -EAGAIN;+	}++	// wake up Rtl8019as+	SetRegPage(3);	+	outportb(CR9346, 0xcf);	//set eem1-0, 11 ,enable write config register+	outportb(CONFIG3, 0x50);//clear pwrdn, sleep mode, set led0 as led_col, led1 as led_crs	+	outportb(CR9346, 0x3f); //disable write config register+	// initialize+	outportb(RstAddr, 0x5a);+	i = 20000;+	while(i--);++	SetRegPage(0);+	inportb(ISR);				+	outportb(BaseAddr, 0x21);   /* set page 0 and stop */+	outportb(Pstart, RPSTART);  /* set Pstart 0x4c */+	outportb(Pstop, RPSTOP);    /* set Pstop 0x80 */+	outportb(BNRY, RPSTART);    /* BNRY-> the last page has been read */	+	outportb(TPSR, SPSTART);    /* SPSTART page start register, 0x40 */+	outportb(RCR, 0xcc);	    /* set RCR 0xcc */	+	outportb(TCR, 0xe0);	    /* set TCR 0xe0 */+	outportb(DCR, 0xc8);	    /* 8bit DMA */+	outportb(IMR, 0x03);	    /* set IMR 0x03, enable tx rx int */+	outportb(ISR, 0xff);	    /* clear ISR */++	SetRegPage(1);+	outportb(PAR0, SrcMacID[0]);+	outportb(PAR1, SrcMacID[1]);+	outportb(PAR2, SrcMacID[2]);+	outportb(PAR3, SrcMacID[3]);+	outportb(PAR4, SrcMacID[4]);+	outportb(PAR6, SrcMacID[5]);+	outportb(CURR, RPSTART+1);	+	outportb(MAR0, 0x00);+	outportb(MAR1, 0x41);+	outportb(MAR2, 0x00);+	outportb(MAR3, 0x80);+	outportb(MAR4, 0x00);+	outportb(MAR5, 0x00);+	outportb(MAR6, 0x00);+	outportb(MAR7, 0x00);+	outportb(BaseAddr, 0x22);		/* set page 0 and start */	+	rBNRY = RPSTART;+	// Start the transmit queue+	//enable_irq(dev->irq);+	netif_start_queue(dev);+        enable_irq(dev->irq);+	return 0;+}++static int nic_8019_stop(struct net_device *dev)+{+	TRACE("stop\n");+	SetRegPage(3);	+	outportb(CR9346, 0xcf);		// set eem1-0, 11 ,enable write config register+	outportb(CONFIG3, 0x66);	// enter pwrdn, sleep mode, set led0 as led_col, led1 as led_crs	+	outportb(CR9346, 0x3f); 	// disable write config register++	free_irq(dev->irq, dev);	+	netif_stop_queue(dev);+	MOD_DEC_USE_COUNT;+	+	return 0;+}++static int nic_8019_start_xmit(struct sk_buff *skb, struct net_device *dev)+{+	int i;+	int len, TxLen;+	u8 *data;++	struct nic_8019_priv *priv = (struct nic_8019_priv *) dev->priv;++	TRACE("start_xmit\n");++	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;+	TRACE("\nTx Length = %i,%x,%x\n", len, skb->data[12], skb->data[13]);+	data = (u8*)skb->data;+			+	outportb(BaseAddr,0x22);  //switch to page 0 and stop remote dma+//	if(inportb(BaseAddr)&4)+//		return 1;	// last remote dma not complete,return 1 echo busy(error),retransmit next++	outportb(RSAR0, 0);+	outportb(RSAR1, SPSTART);+	outportb(RBCR0, len&0xff);	+	outportb(RBCR1, len>>8);			+	outportb(BaseAddr, 0x12);	//begin remote write+	dev->trans_start = jiffies;	+	TxLen=len;+	for(i=0; i<TxLen; i++)    +	{				+		outportb(RWPORT, data[i]);		// copy data to nic ram+		TRACE("%2X,",skb->data[i]);+	}	+			+	TRACE("\n");+	while(inportb(BaseAddr)&4);			// wait for last tx operation end	+	outportb(TPSR,  SPSTART);       // transmit begin page 0x40+	outportb(TBCR0, len&0xff);	+	outportb(TBCR1, len>>8);				+	outportb(BaseAddr, 0x1e);	// begin to send packet	+	dev_kfree_skb(skb);+	return 0;+}++static struct net_device_stats *nic_8019_get_stats(struct net_device *dev)+{+	struct nic_8019_priv *priv = (struct nic_8019_priv *) dev->priv;+	TRACE("get_stats\n");+	return &priv->stats;+}++/******************************************************************************/+static int nic_8019_init(struct net_device *dev)+{+	int i;+	TRACE("init\n");+	ether_setup(dev);	// Assign some of the fields++	// set net_device methods+	dev->open = nic_8019_open;+	dev->stop = nic_8019_stop;+	dev->get_stats = nic_8019_get_stats;+	dev->hard_start_xmit = nic_8019_start_xmit;++	// set net_device data members+	dev->watchdog_timeo = timeout;+	dev->irq = S3C44B0X_INTERRUPT_EINT3;+	dev->dma = 0;++	// set MAC address manually+	printk(KERN_INFO "%s: ", dev->name);+	for(i=0; i<6; i++)+	{+		dev->dev_addr[i] = SrcMacID[i];		+		printk("%2.2x%c", dev->dev_addr[i], (i==5) ? ' ' : ':');+	}+	printk("\n");++	SET_MODULE_OWNER(dev);++	dev->priv = kmalloc(sizeof(struct nic_8019_priv), GFP_KERNEL);+	if(dev->priv == NULL)+		return -ENOMEM;+	memset(dev->priv, 0, sizeof(struct nic_8019_priv));+	spin_lock_init(&((struct nic_8019_priv *) dev->priv)->lock);+	return 0;+}++static struct net_device nic_8019_netdevs = {+	init: nic_8019_init,+};++/*+ * Finally, the module stuff+ */+int __init nic_8019_init_module(void)+{+	int result;+	TRACE("init_module\n");++	//Print version information+	printk(KERN_INFO "%s", version);++	//register_netdev will call nic_8019_init()+	if((result = register_netdev(&nic_8019_netdevs)))+	  printk("Rtl8019as eth: Error %i registering device \"%s\"\n", result, nic_8019_netdevs.name);+	return result ? 0 : -ENODEV;+}++void __exit nic_8019_cleanup(void)+{+	TRACE("cleanup\n");+	kfree(nic_8019_netdevs.priv);+	unregister_netdev(&nic_8019_netdevs);+	return;+}++module_init(nic_8019_init_module);+module_exit(nic_8019_cleanup);++MODULE_DESCRIPTION("Rtl8019as ethernet driver");+MODULE_AUTHOR("antiscle <hzh12@163.net>");+MODULE_LICENSE("GPL");+diff -Nur uClinux-dist.040408.original/linux-2.4.x/drivers/net/rtl8019.h uClinux-dist/linux-2.4.x/drivers/net/rtl8019.h--- uClinux-dist.040408.original/linux-2.4.x/drivers/net/rtl8019.h	1970-01-01 08:00:00.000000000 +0800+++ uClinux-dist/linux-2.4.x/drivers/net/rtl8019.h	2005-03-29 09:57:34.750000000 +0800@@ -0,0 +1,55 @@++#define SHIFT(x)	(x*0x200)++#define	BaseAddr	0x02180000+#define	RWPORT	(BaseAddr+SHIFT(0x10))	/* dma read write address, form 0x10 - 0x17 */+#define	RstAddr (BaseAddr+SHIFT(0x18))	/* reset register, 0x18, 0x1a, 0x1c, 0x1e even address is recommanded */++/* page 0 */+#define	Pstart	(BaseAddr+SHIFT(1))	/* page start */+#define	Pstop	(BaseAddr+SHIFT(2))	/* page stop */+#define	BNRY	(BaseAddr+SHIFT(3))	+#define	TPSR	(BaseAddr+SHIFT(4))	/* transmit page start */+#define	TBCR0	(BaseAddr+SHIFT(5))+#define	TBCR1	(BaseAddr+SHIFT(6))+#define	ISR	(BaseAddr+SHIFT(7))	/* interrupt status register */++#define	RSAR0	(BaseAddr+SHIFT(8))	/* dma read address */+#define	RSAR1	(BaseAddr+SHIFT(9))+#define	RBCR0	(BaseAddr+SHIFT(10))	/* dma read byte count */+#define	RBCR1	(BaseAddr+SHIFT(11))++#define	RCR	(BaseAddr+SHIFT(12))	/* receive config */+#define	TCR	(BaseAddr+SHIFT(13))	/* transmit config */+#define	DCR	(BaseAddr+SHIFT(14))	/* data config */+#define	IMR	(BaseAddr+SHIFT(15))	/* interrupt mask */++#define	ID8019L	(BaseAddr+SHIFT(10))+#define	ID8019H	(BaseAddr+SHIFT(11))++/* page 1 */+#define	PAR0	(BaseAddr+SHIFT(1))+#define	PAR1	(BaseAddr+SHIFT(2))+#define	PAR2	(BaseAddr+SHIFT(3))+#define	PAR3	(BaseAddr+SHIFT(4))+#define	PAR4	(BaseAddr+SHIFT(5))+#define	PAR6	(BaseAddr+SHIFT(6))++#define	CURR	(BaseAddr+SHIFT(7))		+#define	MAR0	(BaseAddr+SHIFT(8))+#define	MAR1	(BaseAddr+SHIFT(9))+#define	MAR2	(BaseAddr+SHIFT(10))+#define	MAR3	(BaseAddr+SHIFT(11))+#define	MAR4	(BaseAddr+SHIFT(12))+#define	MAR5	(BaseAddr+SHIFT(13))+#define	MAR6	(BaseAddr+SHIFT(14))+#define	MAR7	(BaseAddr+SHIFT(15))++/* page 2 */++/* page 3 */+#define	CR9346	(BaseAddr+SHIFT(1))+#define	CONFIG0	(BaseAddr+SHIFT(3))+#define	CONFIG1	(BaseAddr+SHIFT(4))+#define	CONFIG2	(BaseAddr+SHIFT(5))+#define	CONFIG3	(BaseAddr+SHIFT(6))diff -Nur uClinux-dist/linux-2.4.x/drivers/video/s3c44b0xfb.c uClinux-dist/linux-2.4.x/drivers/video.bak/s3c44b0xfb.c--- uClinux-dist/linux-2.4.x/drivers/video/s3c44b0xfb.c	2004-04-08 08:16:56.000000000 +0800+++ uClinux-dist/linux-2.4.x/drivers/video.bak/s3c44b0xfb.c	2005-03-30 16:13:19.906250000 +0800@@ -27,6 +27,7 @@ #include "linux/config.h"  #include <video/fbcon.h>+#include <video/fbcon-cfb8.h> /* add -- luzhl */  #include "s3c44b0xfb.h" #include "asm-armnommu/arch-S3C44B0X/s3c44b0x.h"@@ -73,7 +74,7 @@ 	/* holds the lcd panel name */ 	"LCDBA7T11M4_320x240x8", 	/* clkval */-	15, /* FIXME this is based on a cpu clock of 60,75 MHz */+	4, /* FIXME this is based on a cpu clock of 60,75 MHz */ 	/* Determine the VLINE pulses high level width [clocks] valid values 4, 8, 12 and 16 */ 	16, 	/* Determine the delay between VLINE and VCLOCK [clocks] valid values 4, 8, 12 and 16 */@@ -123,6 +124,7 @@ static struct s3c44b0xfb_info fb_info; static struct s3c44b0xfb_par current_par; static int current_par_valid = 0;+static struct display disp; /* add -- luzhl */  int s3c44b0xfb_init(void); int s3c44b0xfb_setup(char*);@@ -165,7 +167,7 @@  } -static int s3c44b0xfb_decode_var(const struct fb_var_screeninfo *var, void *par,+static int s3c44b0xfb_decode_var(const struct fb_var_screeninfo *var, void *_par, 			       struct fb_info_gen *info) {     /*@@ -177,6 +179,8 @@      *  bitfields, horizontal timing, vertical timing.      */ 	struct known_lcd_panels *p_lcd = &panels[s3c44b0x_lcd_index];+	struct s3c44b0xfb_par *par = (struct s3c44b0xfb_par*)_par;+ 	if (var->xres != p_lcd->width || 	    var->yres != p_lcd->height) 	{@@ -187,6 +191,9 @@ 	{ 		return -EINVAL; 	}++	memcpy(&par->var, var, sizeof(struct fb_var_screeninfo));+ 	return 0;  }@@ -385,7 +392,7 @@ 	return; } -#if 0+#if 1 /* mod -- luzhl */ static void s3c44b0xfb_set_disp(const void *par, struct display *disp, 			      struct fb_info_gen *info) {@@ -398,6 +405,7 @@      *  If you don't have any appropriate operations, you must fill in a      *  pointer to dummy operations, and there will be no text output.      */+ 	return; } #endif@@ -434,9 +442,15 @@ 		modesel = 0; 	} 	helpvalue |=  (modesel & 0x03)<<27; /* MODESEL value */-	helpvalue |= ((fb_info.fb_phys & 0x0FC00000) >> 1); /* LCDBANK addr. */-	helpvalue |= ((fb_info.gen.info.var.xoffset + -		       (fb_info.gen.info.var.yoffset*fb_info.gen.info.var.xres_virtual)) & 0xFFFFF) >> 1;+	/* mod -- luzhl */+	/* helpvalue |= ((fb_info.fb_phys & 0x0FC00000) >> 1); *//* LCDBANK addr. */+	/* helpvalue |= ((fb_info.gen.info.var.xoffset + +		       (fb_info.gen.info.var.yoffset*fb_info.gen.info.var.xres_virtual)) & 0xFFFFF) >> 1; */+	/* add -- luzhl */+	helpvalue |= (fb_info.fb_phys & 0x0FC00000) >> 1;+	helpvalue |= ((fb_info.fb_phys /*+ ((fb_info.gen.info.var.xres_virtual *+				fb_info.gen.info.var.yres_virtual * fb_info.gen.info.var.bits_per_pixel) >> 3)*/)+				& 0x03FFFFF) >> 1; 	outl(helpvalue, S3C44B0X_LCDSADDR1); 	/*---------------------------------*/ 	/* set LCDSADDR2                   */@@ -446,9 +460,15 @@ 	helpvalue |= (p_lcd->mval) << 21; /* MVAL */ 	pagewidth = (p_lcd->width * p_lcd->bpp) >> 4; 	offsize = ((fb_info.gen.info.var.xres_virtual * p_lcd->bpp) >> 4) - pagewidth;-	helpvalue |= (((((fb_info.gen.info.var.xoffset + +	/* mod -- luzhl */+	/* helpvalue |= (((((fb_info.gen.info.var.xoffset +  		       (fb_info.gen.info.var.yoffset*fb_info.gen.info.var.xres_virtual)) & 0xFFFFF) >> 1) +-		       (pagewidth + offsize) * (p_lcd->lineval +1)) & 0xFFFFF); /* LCDBASEL */+		       (pagewidth + offsize) * (p_lcd->lineval +1)) & 0xFFFFF); */ /* LCDBASEL */+	/* add -- luzhl */+	helpvalue |= ((((fb_info.fb_phys /*+ ((fb_info.gen.info.var.xres_virtual *+				fb_info.gen.info.var.yres_virtual * fb_info.gen.info.var.bits_per_pixel) >> 3)*/)+				& 0x03FFFFF) >> 1) + (pagewidth + offsize) * (p_lcd->lineval +1)) & 0x1FFFFF; /* LCDBASEL */+ 	outl(helpvalue, S3C44B0X_LCDSADDR2); 	/*---------------------------------*/ 	/* set LCDSADDR3                   */@@ -529,7 +549,7 @@ 	s3c44b0xfb_setcolreg, 	s3c44b0xfb_pan_display, 	s3c44b0xfb_blank,-	NULL+	s3c44b0xfb_set_disp /* NULL */ /* mod -- luzhl */ };  @@ -546,6 +566,7 @@ 	struct known_lcd_panels *p_lcd; 	int num_panels; /* number of known LCD panels */ 	int i;+	char *fbuf; /* add -- luzhl */  	printk("S3C44B0X framebuffer init\n"); @@ -581,23 +602,24 @@  	p_lcd = &panels[s3c44b0x_lcd_index]; +/* add luzhl */+	fbuf = kmalloc((p_lcd->width * p_lcd->height * p_lcd->bpp) >> 3, GFP_KERNEL);+	if(!fbuf)+		return -ENOMEM;+ 	memset(&fb_info.gen, 0, sizeof(fb_info.gen)); 	fb_info.gen.fbhw = &s3c44b0xfb_switch; 	sprintf(fb_info.gen.info.modename, "%dx%dx%d",p_lcd->width,p_lcd->height,p_lcd->bpp); 	fb_info.gen.parsize = sizeof(struct s3c44b0xfb_par);+	fb_info.gen.info.screen_base = fbuf; /* add -- luzhl */ 	fb_info.gen.info.changevar = NULL; 	fb_info.gen.info.node = -1; 	fb_info.gen.info.fbops = &s3c44b0xfb_ops;-	fb_info.gen.info.disp = NULL; /* not needed ?? */+	fb_info.gen.info.disp = &disp; /* mod -- luzhl */ /* NULL; */ /* not needed ?? */ 	fb_info.gen.info.switch_con = NULL; 	fb_info.gen.info.updatevar = NULL; 	fb_info.gen.info.blank = &s3c44b0xfb_gen_blank; 	fb_info.gen.info.flags = FBINFO_FLAG_DEFAULT;-	/* This should give a reasonable default video mode */-	/* fbgen_get_var(&disp.var, -1, &fb_info.gen.info); */-	/* fbgen_do_set_var(&disp.var, 1, &fb_info.gen); */-	/* fbgen_set_disp(-1, &fb_info.gen); */-	/* fbgen_install_cmap(0, &fb_info.gen); */  	/********************************************** 	 * file the var struct inside the current_par struct@@ -637,7 +659,7 @@ 	 */ 	fb_info.fb_size = (p_lcd->width * p_lcd->height * p_lcd->bpp) >> 3; 	/* FIXME align it to 4 MB */-	fb_info.fb_phys = S3C44B0X_FB_ADDRESS;+	fb_info.fb_phys = fbuf; 	fb_info.fb_virt_start = fb_info.fb_phys; 	current_par.line_length = (p_lcd->width * p_lcd->bpp) >> 3; @@ -647,10 +669,24 @@ 	/* fill the fix element of fb_info.gen.info */ 	s3c44b0xfb_encode_fix(&fb_info.gen.info.fix, &current_par, &fb_info.gen);