library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lv18_ctl is
	port(
		grst 					: in std_logic;
		fosc120m  			: in std_logic;
		rclk 					: in std_logic;
		mode1 				: in std_logic;
		mode2 				: in std_logic;
		mode4 				: in std_logic;
		lock 					: in std_logic;
		rout 					: in std_logic_vector(17 downto 0); 
		ren 					: out std_logic;
		den 					: out std_logic;
		rpwdn 				: out std_logic;
		tpwdn 				: out std_logic; 
		line_le 				: out std_logic;
		local_le 			: out std_logic; 
		wrfifo 				: out std_logic;
		fifodin 				: out std_logic_vector(9 downto 0);
		ws 					: out std_logic_vector(7 downto 0);
		sigb 					: out std_logic;
		sigp 					: out std_logic;
		sigs 					: out std_logic;
		sigf 					: out std_logic;
		reset_f 				: out std_logic;
		erase_f 				: out std_logic;
		j_reset 				: out std_logic;
		j_set 				: out std_logic;
		equal 				: out std_logic;
		we_f 					: out std_logic;
		auto_f 				: out std_logic;
		manual_f 			: out std_logic;
		sinwave_f 			: out std_logic
		);
end lv18_ctl;

architecture Behavioral of lv18_ctl is
	signal f_rout 				: std_logic_vector(17 downto 0);
	signal card_addr 			: std_logic_vector(3 downto 0);
	signal equal_f 			: std_logic;
	signal f_rclk 				: std_logic;
	signal rclk_count 		: std_logic_vector(1 downto 0);
	signal f_lock 				: std_logic;
	signal f_mode1				: std_logic;
	signal mode1_count		: std_logic_vector(3 downto 0);
	signal f_mode2				: std_logic;
	signal mode2_count		: std_logic_vector(3 downto 0);
	signal lock_count 		: std_logic_vector(1 downto 0);
	signal f_area 				: std_logic_vector(1 downto 0);
	 type step is (step0,step1,step2,step3,step4,step5,step6,step7,step8,step9);	 
		signal step_state					:step; 			

begin
------------------------120M fosc--------------------------------------------
	card_addr <= "1001";    -------------------配置卡地址
	equal <= equal_f;
	ren <= '1';
	den <= '1';
	tpwdn <= '1';
	rpwdn <= '1';
	line_le <= '1';																				                                                                                                                                                                      
	local_le <= '0';
main:process(grst,fosc120m)
	begin
		if grst = '0' then
			wrfifo <= '1';
			reset_f <= '0';
			equal_f <= '0';
			erase_f <= '0';
			we_f <= '0';
			auto_f <= '0';
			manual_f <= '0';
			sinwave_f <= '0';
			step_state <= step0;
			sigb <= '0';  ----????????????????????	sigb <= '1';
			sigp <= '0';
			sigs <= '0';
			sigf <= '0';
			ws <= "00000000";
		elsif fosc120m'event and fosc120m = '1' then
			if mode4 = '0' then
				case step_state is
					when step0 =>
						wrfifo <= '1';
						reset_f <= '0';
						equal_f <= '0';
						erase_f <= '0';
						we_f <= '0';
						auto_f <= '0';
						manual_f <= '0';
						sinwave_f <= '0';
						equal_f <= '0';
						step_state <= step1;
					when step1 =>
						if f_lock = '0' then
							step_state <= step2;
						else
							step_state <= step1;
						end if;
					when step2 =>
						if f_rclk = '0' then			
							step_state <= step3;
						else
							step_state <= step2;
						end if;
					when step3 =>
						if f_rclk = '1' then							
							step_state <= step4;
						else
							step_state <= step3;
						end if;
					when step4 =>
						f_rout <= rout;
						step_state <= step5;
					when step5 => 							 
						fifodin(9 downto 8)	<= f_rout (17 downto 16);
						fifodin(7 downto 0)	<= f_rout (7 downto 0);
						if f_rout(17 downto 16) = "11"	then
							 step_state <= step2;
							if f_rout(4 downto 0) = "00000" then		--reset  														   
									reset_f <= '1';
									equal_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '0';
									manual_f <= '0';
									sinwave_f <= '0';
									sigb <= '0';
									sigp <= '0';
									sigs <= '0';
									sigf <= '0';
									ws <= "00000000";
							elsif f_rout(4 downto 0) = "00001" then	 ---erase									
									reset_f <= '0';
									erase_f <= '1';
									we_f <= '0';
									auto_f <= '0';
									manual_f <= '0';
									sinwave_f <= '0';
									ws <= "00000000";
							elsif f_rout(4 downto 0) = "00010" then	---we
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '1';
									auto_f <= '0';
									manual_f <= '0';
									sinwave_f <= '0';
									ws <= "00000000";
							elsif f_rout(4 downto 0) = "10000" then	 --auto work pattern	dian pin
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '1';
									manual_f <= '0';
									sinwave_f <= '0';
									ws <= "00010000";
							elsif f_rout(4 downto 0) = "11000" then	 --auto work pattern	tiao pin
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '1';
									manual_f <= '0';
									sinwave_f <= '0';
									ws <= "00011000";
							elsif f_rout(4 downto 0) = "10001" then	--manual work pattern  dian pin
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '0';
									manual_f <= '1';
									sinwave_f <= '0';
									ws <= "00010001";
							elsif f_rout(4 downto 0) = "11001" then	--manual work pattern  tiao pin
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '0';
									manual_f <= '1';
									sinwave_f <= '0';
									ws <= "00011001";
							elsif f_rout(4 downto 0) = "10010" then	 --sinwave work pattern
									reset_f <= '0';
									erase_f <= '0';
									we_f <= '0';
									auto_f <= '0';
									manual_f <= '0';
									sinwave_f <= '1';
									ws <= "00010010";
							end if;
						elsif f_rout(17 downto 16) = "01"  then 							 
							if f_rout(3 downto 0) = card_addr then
								f_area <= f_rout(5 downto 4); 
								equal_f <= '1';
							else
								equal_f <= '0';
							end if;
							step_state <= step6;
						elsif f_rout(17 downto 16) = "10" and equal_f = '1' then
							step_state <= step7;
						else
							step_state <= step2;
						end if;
				   when step6 =>
						if f_area = "00"  then
							sigb <= '1';
							sigp <= '0';
							sigs <= '0';
							sigf <= '0';
						elsif f_area = "01"then
							sigb <= '0';
							sigp <= '1';
							sigs <= '0';
							sigf <= '0';
						elsif f_area = "10" then
							sigb <= '0';
							sigp <= '0';
							sigs <= '1';
							sigf <= '0';	
						elsif f_area = "11" then
							sigb <= '0';
							sigp <= '0';
							sigs <= '0';
							sigf <= '1';
						end if;
						step_state <= step2;
					when step7 =>
						wrfifo <= '0';
						step_state <= step8;
					when step8 =>
						wrfifo <= '1';
						step_state <= step2;
					when others =>
						step_state <= step0;
				end case;
			else
				step_state <= step0;	
			end if;
		end if;
	end process main; 
-------------------------xiao dou rclk-------------------------------  
	p1: process(grst, fosc120m)
	begin
		if grst='0' then
				rclk_count<="00";
				f_rclk<='1';
		elsif fosc120m ' event and fosc120m='1' then
				if rclk='0' and rclk_count(1)='0' and f_rclk='1' then
					f_rclk<='1';
					rclk_count<=rclk_count+1;
				elsif rclk='0' and rclk_count(1)='1' and f_rclk='1' then
					f_rclk<='0';
					rclk_count<="00";
				elsif rclk='1' and rclk_count(1)='0' and f_rclk='0' then
					f_rclk<='0';
					rclk_count<=rclk_count+1;
				elsif rclk='1' and rclk_count(1)='1' and f_rclk='0' then
					f_rclk<='1';
					rclk_count<="00";
				else
					rclk_count<="00";
				end if;
		end if;
	end process p1;
-----------------------------xiao dou lock---------------------
	p2: process(grst, fosc120m)
	begin
		if grst='0' then
				lock_count<="00";
				f_lock<='1';
		elsif fosc120m ' event and fosc120m='1' then
				if lock='0' and lock_count(1)='0' and f_lock='1' then
					f_lock<='1';
					lock_count<=lock_count+1;
				elsif lock='0' and lock_count(1)='1' and f_lock='1' then
					f_lock<='0';
					lock_count<="00";
				elsif lock='1' and lock_count(1)='0' and f_lock='0' then
					f_lock<='0';
					lock_count<=lock_count+1;
				elsif lock='1' and lock_count(1)='1' and f_lock='0' then
					f_lock<='1';
					lock_count<="00";
				else
					lock_count<="00";
				end if;
		end if;
	end process p2;
---------------------------j_reset & j_set-----------------------------
	p3: process(grst,f_mode1,f_mode2)
	begin
		if grst = '0' then
			j_reset <= '0';
			j_set <= '1';
		elsif f_mode1 = '1' or f_mode2 = '1' then
			j_reset <= '1';
			j_set <= '0';
		else
			j_reset <= '0';
			j_set <= '1';
		end if;			
	end process p3;
	-----------------------------xiao dou mode1---------------------
	p4: process(grst, fosc120m)
	begin
		if grst='0' then
				mode1_count<="0000";
				f_mode1<='0';
		elsif fosc120m ' event and fosc120m='1' then
				if mode1='0' and mode1_count(3)='0' and f_mode1='1' then
					f_mode1<='1';
					mode1_count<=mode1_count+1;
				elsif mode1='0' and mode1_count(3)='1' and f_mode1='1' then
					f_mode1<='0';
					mode1_count<="0000";
				elsif mode1='1' and mode1_count(3)='0' and f_mode1='0' then
					f_mode1<='0';
					mode1_count<=mode1_count+1;
				elsif mode1='1' and mode1_count(3)='1' and f_mode1='0' then
					f_mode1<='1';
					mode1_count<="0000";
				else
					mode1_count<="0000";
				end if;
		end if;
	end process p4;
		-----------------------------xiao dou mode2---------------------
	p5: process(grst, fosc120m)
	begin
		if grst='0' then
				mode2_count<="0000";
				f_mode2<='0';
		elsif fosc120m ' event and fosc120m='1' then
				if mode2='0' and mode2_count(3)='0' and f_mode2='1' then
					f_mode2<='1';
					mode2_count<=mode2_count+1;
				elsif mode2='0' and mode2_count(3)='1' and f_mode2='1' then
					f_mode2<='0';
					mode2_count<="0000";
				elsif mode2='1' and mode2_count(3)='0' and f_mode2='0' then
					f_mode2<='0';
					mode2_count<=mode2_count+1;
				elsif mode2='1' and mode2_count(3)='1' and f_mode2='0' then
					f_mode2<='1';
					mode2_count<="0000";
				else
					mode2_count<="0000";
				end if;
		end if;
	end process p5;


 
end Behavioral;