Release 7.1i par H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.B5A6955F24534CE::  Tue Sep 30 09:54:31 2008par -w -intstyle ise -ol high -t 1 -n 3 rece_map.ncd mppr_result.dir rece.pcf Constraints file: rece.pcf.   "rece" is an NCD, version 3.1, device xc2s100e, package tq144, speed -6Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)Device speed data version:  "PRODUCTION 1.18 2005-01-22".Device Utilization Summary:   Number of DLLs                      1 out of 4      25%   Number of GCLKs                     1 out of 4      25%   Number of External GCLKIOBs         1 out of 4      25%      Number of LOCed GCLKIOBs         1 out of 1     100%   Number of External IOBs            28 out of 98     28%      Number of LOCed IOBs            28 out of 28    100%   Number of SLICEs                   42 out of 1200    3%Overall effort level (-ol):   High (set by user)Placer effort level (-pl):    High (set by user)Placer cost table entry (-t): 3Router effort level (-rl):    High (set by user)WARNING:Par:276 - The signal rclk_IBUF has no loadStarting PlacerPhase 1.1Phase 1.1 (Checksum:989823) REAL time: 0 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs Phase 3.23Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 0 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs Phase 6.8.....Phase 6.8 (Checksum:9a1d69) REAL time: 0 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 1 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 1 secs Writing design to file mppr_result.dir/H_H_3.ncdTotal REAL time to Placer completion: 1 secs Total CPU time to Placer completion: 0 secs Starting RouterPhase 1: 220 unrouted;       REAL time: 1 secs Phase 2: 174 unrouted;       REAL time: 2 secs Phase 3: 8 unrouted;       REAL time: 2 secs Phase 4: 8 unrouted; (673)      REAL time: 2 secs Phase 5: 8 unrouted; (0)      REAL time: 2 secs Phase 6: 0 unrouted; (0)      REAL time: 2 secs Phase 7: 0 unrouted; (0)      REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|         refclk_OBUF |      GCLKBUF1| No   |   29 |  0.133     |  0.491      |+---------------------+--------------+------+------+------------+-------------+   The Delay Summary ReportThe NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0   The AVERAGE CONNECTION DELAY for this design is:        0.804   The MAXIMUM PIN DELAY IS:                               3.886   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.834   Listing Pin Delays by value: (nsec)    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00   ---------   ---------   ---------   ---------   ---------   ---------         146          37          16           3           0           0Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 2 secs Total CPU time to PAR completion: 2 secs Peak Memory Usage:  78 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 1Number of info messages: 0Writing design to file mppr_result.dir/H_H_3.ncdPAR done!