library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_depart is
	port(
		datain	:	in	std_logic_vector(7 downto 0);
		data0out	:	out	std_logic_vector(3 downto 0);
		data1out	:	out	std_logic_vector(3 downto 0)
	--	data2out	:	out	std_logic_vector(3 downto 0);
	--	data3out	:	out	std_logic_vector(3 downto 0)
		);
end data_depart;

architecture Behavioral of data_depart is

begin
	data0out <= datain(3 downto 0);
	data1out <= datain(7 downto 4);
--	data2out <= datain(11 downto 8);
--	data3out <= datain(15 downto 12);
end Behavioral;