Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 1.25 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 1.25 s | Elapsed : 0.00 / 1.00 s --> Reading design: grst.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "grst.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "grst"Output Format                      : NGCTarget Device                      : xc2s100e-6-tq144---- Source OptionsTop Module Name                    : grstAutomatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : grst.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOtristate2logic                     : Yesuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/dd.vhd" in Library work.Architecture behavioral of Entity grst is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <grst> (Architecture <behavioral>).Entity <grst> analyzed. Unit <grst> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <grst>.    Related source file is "D:/2222/dd.vhd".    Found 1-bit register for signal <grst>.    Found 23-bit comparator less for signal <$n0001> created at line 20.    Found 23-bit up counter for signal <cnt>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <grst> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters                         : 1 23-bit up counter                 : 1# Registers                        : 1 1-bit register                    : 1# Comparators                      : 1 23-bit comparator less            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <grst> ...Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block grst, actual ratio is 2.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : grst.ngrTop Level Output File Name         : grstOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 2Macro Statistics :# Registers                        : 2#      1-bit register              : 1#      23-bit register             : 1# Adders/Subtractors               : 1#      23-bit adder                : 1# Comparators                      : 1#      23-bit comparator less      : 1Cell Usage :# BELS                             : 96#      GND                         : 1#      INV                         : 8#      LUT1                        : 10#      LUT1_L                      : 14#      LUT2_L                      : 2#      LUT3_L                      : 3#      LUT4_L                      : 1#      MUXCY                       : 34#      VCC                         : 1#      XORCY                       : 22# FlipFlops/Latches                : 24#      FDE                         : 23#      FDR                         : 1# Clock Buffers                    : 1#      BUFGP                       : 1# IO Buffers                       : 1#      OBUF                        : 1=========================================================================Device utilization summary:---------------------------Selected Device : 2s100etq144-6  Number of Slices:                      37  out of   1200     3%   Number of Slice Flip Flops:            24  out of   2400     1%   Number of 4 input LUTs:                30  out of   2400     1%   Number of bonded IOBs:                  2  out of    102     1%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+fosc60m                            | BUFGP                  | 24    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 8.288ns (Maximum Frequency: 120.656MHz)   Minimum input arrival time before clock: No path found   Maximum output required time after clock: 6.514ns   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================Timing constraint: Default period analysis for Clock 'fosc60m'  Clock period: 8.288ns (frequency: 120.656MHz)  Total number of paths / destination ports: 828 / 47-------------------------------------------------------------------------Delay:               8.288ns (Levels of Logic = 14)  Source:            cnt_0 (FF)  Destination:       cnt_21 (FF)  Source Clock:      fosc60m rising  Destination Clock: fosc60m rising  Data Path: cnt_0 to cnt_21                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDE:C->Q              2   0.992   1.150  cnt_0 (cnt_0)     LUT4_L:I0->LO         1   0.468   0.000  Andlut (N3)     MUXCY:S->O            1   0.515   0.000  Andcy (And_cyo)     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_0 (And_cyo1)     MUXCY:CI->O           1   0.058   0.000  norcy (nor_cyo)     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_1 (And_cyo2)     MUXCY:CI->O           1   0.058   0.000  norcy_rn_0 (nor_cyo1)     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_2 (And_cyo3)     MUXCY:CI->O           1   0.058   0.000  norcy_rn_1 (nor_cyo2)     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_3 (And_cyo4)     MUXCY:CI->O           1   0.058   0.000  norcy_rn_2 (nor_cyo3)     MUXCY:CI->O           1   0.058   0.000  Andcy_rn_4 (And_cyo5)     MUXCY:CI->O           1   0.058   0.000  norcy_rn_3 (nor_cyo4)     MUXCY:CI->O           3   0.058   1.320  Andcy_rn_5 (And_cyo6)     INV:I->O              8   0.468   2.050  And_cyo6_INV_INV_0 (_n0001)     FDE:CE                    0.687          cnt_10    ----------------------------------------    Total                      8.288ns (3.768ns logic, 4.520ns route)                                       (45.5% logic, 54.5% route)=========================================================================Timing constraint: Default OFFSET OUT AFTER for Clock 'fosc60m'  Total number of paths / destination ports: 1 / 1-------------------------------------------------------------------------Offset:              6.514ns (Levels of Logic = 1)  Source:            grst (FF)  Destination:       grst (PAD)  Source Clock:      fosc60m rising  Data Path: grst to grst                                Gate     Net    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)    ----------------------------------------  ------------     FDR:C->Q              1   0.992   0.920  grst (grst_OBUF)     OBUF:I->O                 4.602          grst_OBUF (grst)    ----------------------------------------    Total                      6.514ns (5.594ns logic, 0.920ns route)                                       (85.9% logic, 14.1% route)=========================================================================CPU : 4.25 / 5.70 s | Elapsed : 4.00 / 5.00 s --> Total memory usage is 88636 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)