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-- Company: 
-- Engineer:
--
-- Create Date:    16:08:51 01/19/06
-- Design Name:    
-- Module Name:    data_split - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_split is
	port	(
			 di			: in std_logic_vector(7 downto 0);
			 wrdat0		: out std_logic;
			 wrdat1		: out std_logic;
			 wrdat2		: out std_logic;
			 wrdat3		: out std_logic;
			 wrdat4		: out std_logic;
			 wrdat5		: out std_logic;
			 wrdat6		: out std_logic;
			 wrdat7		: out std_logic
			);

end data_split;

architecture Behavioral of data_split is

begin
	wrdat0<=di(0);
	wrdat1<=di(1);
	wrdat2<=di(2);
	wrdat3<=di(3);
	wrdat4<=di(4);
	wrdat5<=di(5);
	wrdat6<=di(6);
	wrdat7<=di(7);
	
	--dqo<=di(7 downto 4);
end Behavioral;