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Release 7.1i Trace H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -ise d:\2222\2222.ise -intstyle ise -e 3 -l 3 -s 6
-xml fifo12bit_2k fifo12bit_2k.ncd -o fifo12bit_2k.twr fifo12bit_2k.pcf


Design file:              fifo12bit_2k.ncd
Physical constraint file: fifo12bit_2k.pcf
Device,speed:             xc2s100e,-6 (PRODUCTION 1.18 2005-01-22)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock fiford
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
addb<0>     |    6.178(R)|   -3.109(R)|fiford_BUFGP      |   0.000|
addb<10>    |    4.649(R)|   -2.733(R)|fiford_BUFGP      |   0.000|
addb<1>     |    7.366(R)|   -1.268(R)|fiford_BUFGP      |   0.000|
addb<2>     |    7.972(R)|   -1.248(R)|fiford_BUFGP      |   0.000|
addb<3>     |    6.714(R)|   -0.505(R)|fiford_BUFGP      |   0.000|
addb<4>     |    8.232(R)|   -1.293(R)|fiford_BUFGP      |   0.000|
addb<5>     |    4.470(R)|   -2.313(R)|fiford_BUFGP      |   0.000|
addb<6>     |    7.571(R)|   -1.275(R)|fiford_BUFGP      |   0.000|
addb<7>     |    4.258(R)|   -1.740(R)|fiford_BUFGP      |   0.000|
addb<8>     |    4.957(R)|   -2.769(R)|fiford_BUFGP      |   0.000|
addb<9>     |    4.422(R)|   -2.177(R)|fiford_BUFGP      |   0.000|
datain<0>   |    2.921(R)|   -1.879(R)|fiford_BUFGP      |   0.000|
datain<10>  |    1.768(R)|   -0.726(R)|fiford_BUFGP      |   0.000|
datain<11>  |    2.578(R)|   -1.536(R)|fiford_BUFGP      |   0.000|
datain<1>   |    5.086(R)|   -4.044(R)|fiford_BUFGP      |   0.000|
datain<2>   |    2.529(R)|   -1.487(R)|fiford_BUFGP      |   0.000|
datain<3>   |    2.537(R)|   -1.495(R)|fiford_BUFGP      |   0.000|
datain<4>   |    1.828(R)|   -0.786(R)|fiford_BUFGP      |   0.000|
datain<5>   |    2.539(R)|   -1.497(R)|fiford_BUFGP      |   0.000|
datain<6>   |    2.855(R)|   -1.813(R)|fiford_BUFGP      |   0.000|
datain<7>   |    2.693(R)|   -1.651(R)|fiford_BUFGP      |   0.000|
datain<8>   |    2.960(R)|   -1.918(R)|fiford_BUFGP      |   0.000|
datain<9>   |    3.316(R)|   -2.274(R)|fiford_BUFGP      |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock fifowr
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
adda<0>     |    5.656(R)|   -3.988(R)|fifowr_BUFGP      |   0.000|
adda<10>    |    6.587(R)|   -3.815(R)|fifowr_BUFGP      |   0.000|
adda<1>     |    5.528(R)|   -3.851(R)|fifowr_BUFGP      |   0.000|
adda<2>     |    6.120(R)|   -3.224(R)|fifowr_BUFGP      |   0.000|
adda<3>     |    6.321(R)|   -3.576(R)|fifowr_BUFGP      |   0.000|
adda<4>     |    7.173(R)|   -2.547(R)|fifowr_BUFGP      |   0.000|
adda<5>     |    7.371(R)|   -2.157(R)|fifowr_BUFGP      |   0.000|
adda<6>     |    6.561(R)|   -2.934(R)|fifowr_BUFGP      |   0.000|
adda<7>     |    7.863(R)|   -0.534(R)|fifowr_BUFGP      |   0.000|
adda<8>     |    4.934(R)|   -2.187(R)|fifowr_BUFGP      |   0.000|
adda<9>     |    7.823(R)|   -0.402(R)|fifowr_BUFGP      |   0.000|
datain<0>   |    2.921(R)|   -1.879(R)|fifowr_BUFGP      |   0.000|
datain<10>  |    1.768(R)|   -0.726(R)|fifowr_BUFGP      |   0.000|
datain<11>  |    2.578(R)|   -1.536(R)|fifowr_BUFGP      |   0.000|
datain<1>   |    3.984(R)|   -2.942(R)|fifowr_BUFGP      |   0.000|
datain<2>   |    2.529(R)|   -1.487(R)|fifowr_BUFGP      |   0.000|
datain<3>   |    2.537(R)|   -1.495(R)|fifowr_BUFGP      |   0.000|
datain<4>   |    1.828(R)|   -0.786(R)|fifowr_BUFGP      |   0.000|
datain<5>   |    2.539(R)|   -1.497(R)|fifowr_BUFGP      |   0.000|
datain<6>   |    2.534(R)|   -1.492(R)|fifowr_BUFGP      |   0.000|
datain<7>   |    2.693(R)|   -1.651(R)|fifowr_BUFGP      |   0.000|
datain<8>   |    2.960(R)|   -1.918(R)|fifowr_BUFGP      |   0.000|
datain<9>   |    3.316(R)|   -2.274(R)|fifowr_BUFGP      |   0.000|
------------+------------+------------+------------------+--------+

Clock fiford to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
dataout<0>  |   14.055(R)|fiford_BUFGP      |   0.000|
dataout<10> |   12.649(R)|fiford_BUFGP      |   0.000|
dataout<11> |   11.047(R)|fiford_BUFGP      |   0.000|
dataout<1>  |   13.743(R)|fiford_BUFGP      |   0.000|
dataout<2>  |   12.664(R)|fiford_BUFGP      |   0.000|
dataout<3>  |   12.670(R)|fiford_BUFGP      |   0.000|
dataout<4>  |   12.631(R)|fiford_BUFGP      |   0.000|
dataout<5>  |   12.721(R)|fiford_BUFGP      |   0.000|
dataout<6>  |   12.558(R)|fiford_BUFGP      |   0.000|
dataout<7>  |   12.252(R)|fiford_BUFGP      |   0.000|
dataout<8>  |   13.580(R)|fiford_BUFGP      |   0.000|
dataout<9>  |   13.678(R)|fiford_BUFGP      |   0.000|
------------+------------+------------------+--------+

Analysis completed Mon Oct 13 11:06:12 2008
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Peak Memory Usage: 69 MB