Release 7.1i Map H.38Xilinx Mapping Report File for Design 'fentclk'Design Information------------------Command Line   : D:/Xilinx/bin/nt/map.exe -ise d:\2222\2222.ise -intstyle ise -p
xc2s100e-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o fentclk_map.ncd
fentclk.ngd fentclk.pcf Target Device  : xc2s100eTarget Package : tq144Target Speed   : -6Mapper Version : spartan2e -- $Revision: 1.26.6.3 $Mapped Date    : Mon Sep 29 16:14:11 2008Design Summary--------------Number of errors:      0Number of warnings:    0Logic Utilization:  Number of Slice Flip Flops:         3 out of  2,400    1%  Number of 4 input LUTs:             2 out of  2,400    1%Logic Distribution:    Number of occupied Slices:                           2 out of  1,200    1%    Number of Slices containing only related logic:      2 out of      2  100%    Number of Slices containing unrelated logic:         0 out of      2    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs:         2 out of  2,400    1%   Number of bonded IOBs:             2 out of     98    2%      IOB Flip Flops:                               1   Number of GCLKs:                   1 out of      4   25%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  44Additional JTAG gate count for IOBs:  144Peak Memory Usage:  97 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   ||                                    |         |           |             | Strength | Rate |          |          | Delay |+------------------------------------------------------------------------------------------------------------------------+| fosc60m                            | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       || grst                               | IOB     | INPUT     | LVTTL       |          |      |          |          |       || refclk                             | IOB     | OUTPUT    | LVTTL       | 12       | SLOW | OUTFF    |          |       |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 3Number of Equivalent Gates for Design = 44Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 1GCLKs = 1Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 2IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 1IOB Flip Flops = 1Unbonded IOBs = 0Bonded IOBs = 2XORs = 0CARRY_INITs = 0CARRY_SKIPs = 0CARRY_MUXes = 0Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 04 input LUTs = 2Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 1Slice Flip Flops = 3Slices = 2F6 Muxes = 0F5 Muxes = 0Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 0Number of LUT signals with 1 load = 2NGM Average fanout of LUT = 1.00NGM Maximum fanout of LUT = 1NGM Average fanin for LUT = 2.5000Number of LUT symbols = 2