Release 7.1i - xst H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.--> Parameter TMPDIR set to __projnavCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 0.47 s | Elapsed : 0.00 / 0.00 s --> Reading design: clk60.prjTABLE OF CONTENTS  1) Synthesis Options Summary  2) HDL Compilation  3) HDL Analysis  4) HDL Synthesis  5) Advanced HDL Synthesis     5.1) HDL Synthesis Report  6) Low Level Synthesis  7) Final Report     7.1) Device utilization summary     7.2) TIMING REPORT=========================================================================*                      Synthesis Options Summary                        *=========================================================================---- Source ParametersInput File Name                    : "clk60.prj"Input Format                       : mixedIgnore Synthesis Constraint File   : NO---- Target ParametersOutput File Name                   : "clk60"Output Format                      : NGCTarget Device                      : xc2s100e-6-tq144---- Source OptionsTop Module Name                    : clk60Automatic FSM Extraction           : YESFSM Encoding Algorithm             : AutoFSM Style                          : lutRAM Extraction                     : YesRAM Style                          : AutoROM Extraction                     : YesROM Style                          : AutoMux Extraction                     : YESDecoder Extraction                 : YESPriority Encoder Extraction        : YESShift Register Extraction          : YESLogical Shifter Extraction         : YESXOR Collapsing                     : YESResource Sharing                   : YESMultiplier Style                   : lutAutomatic Register Balancing       : No---- Target OptionsAdd IO Buffers                     : YESGlobal Maximum Fanout              : 100Add Generic Clock Buffer(BUFG)     : 4Register Duplication               : YESEquivalent register Removal        : YESSlice Packing                      : YESPack IO Registers into IOBs        : auto---- General OptionsOptimization Goal                  : SpeedOptimization Effort                : 1Keep Hierarchy                     : NOGlobal Optimization                : AllClockNetsRTL Output                         : YesWrite Timing Constraints           : NOHierarchy Separator                : /Bus Delimiter                      : <>Case Specifier                     : maintainSlice Utilization Ratio            : 100Slice Utilization Ratio Delta      : 5---- Other Optionslso                                : clk60.lsoRead Cores                         : YEScross_clock_analysis               : NOverilog2001                        : YESsafe_implementation                : NoOptimize Instantiated Primitives   : NOtristate2logic                     : Yesuse_clock_enable                   : Yesuse_sync_set                       : Yesuse_sync_reset                     : Yesenable_auto_floorplanning          : No==================================================================================================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/clk60.vhf" in Library work.Architecture behavioral of Entity clk60 is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <clk60> (Architecture <behavioral>).    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <XLXI_1> in unit <clk60>.    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <XLXI_1> in unit <clk60>.Entity <clk60> analyzed. Unit <clk60> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <clk60>.    Related source file is "D:/2222/clk60.vhf".Unit <clk60> synthesized.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <clk60> ...Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk60, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : clk60.ngrTop Level Output File Name         : clk60Output Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 2Cell Usage :# BELS                             : 1#      GND                         : 1# Clock Buffers                    : 1#      BUFG                        : 1# IO Buffers                       : 2#      IBUFG                       : 1#      OBUF                        : 1# DLLs                             : 1#      CLKDLL                      : 1=========================================================================Device utilization summary:---------------------------Selected Device : 2s100etq144-6  Number of bonded IOBs:                  2  out of    102     1%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6   Minimum period: No path found   Minimum input arrival time before clock: No path found   Maximum output required time after clock: No path found   Maximum combinational path delay: No path foundTiming Detail:--------------All values displayed in nanoseconds (ns)=========================================================================CPU : 3.20 / 3.73 s | Elapsed : 3.00 / 3.00 s --> Total memory usage is 88636 kilobytesNumber of errors   :    0 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)