--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 7.1i
--  \   \         Application : sch2vhdl
--  /   /         Filename : rece.vhf
-- /___/   /\     Timestamp : 09/29/2008 16:43:56
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: D:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family spartan2e -flat -suppress -w rece.sch rece.vhf
--Design Name: rece
--Device: spartan2e
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity rece is
   port ( fosc     : in    std_logic; 
          lock     : in    std_logic; 
          rclk     : in    std_logic; 
          rout     : in    std_logic_vector (17 downto 0); 
          den      : out   std_logic; 
          led1     : out   std_logic; 
          line_le  : out   std_logic; 
          local_le : out   std_logic; 
          refclk   : out   std_logic; 
          ren      : out   std_logic; 
          rpwdn    : out   std_logic; 
          tpwdn    : out   std_logic);
end rece;

architecture BEHAVIORAL of rece is
   signal XLXN_2       : std_logic;
   signal refclk_DUMMY : std_logic;
   component grst
      port ( fosc60m : in    std_logic; 
             grst    : out   std_logic);
   end component;
   
   component clk60
      port ( fosc    : in    std_logic; 
             fosc60m : out   std_logic);
   end component;
   
   component rece18
      port ( grst     : in    std_logic; 
             fosc60m  : in    std_logic; 
             rclk     : in    std_logic; 
             lock     : in    std_logic; 
             rout     : in    std_logic_vector (17 downto 0); 
             ren      : out   std_logic; 
             den      : out   std_logic; 
             rpwdn    : out   std_logic; 
             tpwdn    : out   std_logic; 
             line_le  : out   std_logic; 
             led1     : out   std_logic; 
             local_le : out   std_logic);
   end component;
   
begin
   refclk <= refclk_DUMMY;
   XLXI_2 : grst
      port map (fosc60m=>refclk_DUMMY,
                grst=>XLXN_2);
   
   XLXI_3 : clk60
      port map (fosc=>fosc,
                fosc60m=>refclk_DUMMY);
   
   XLXI_4 : rece18
      port map (fosc60m=>refclk_DUMMY,
                grst=>XLXN_2,
                lock=>lock,
                rclk=>rclk,
                rout(17 downto 0)=>rout(17 downto 0),
                den=>den,
                led1=>led1,
                line_le=>line_le,
                local_le=>local_le,
                ren=>ren,
                rpwdn=>rpwdn,
                tpwdn=>tpwdn);
   
end BEHAVIORAL;