==========================*                            HDL Analysis                               *=========================================================================Analyzing Entity <rece18> (Architecture <behavioral>).Entity <rece18> analyzed. Unit <rece18> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <rece18>.    Related source file is "D:/2222/rece18.vhd".WARNING:Xst:737 - Found 1-bit latch for signal <led1>.    Found 8-bit adder for signal <$n0007> created at line 76.    Found 2-bit adder for signal <$n0011> created at line 111.    Found 8-bit comparator equal for signal <$n0012> created at line 82.    Found 8-bit register for signal <a>.    Found 8-bit register for signal <b>.    Found 18-bit register for signal <f_datain>.    Found 1-bit register for signal <f_rclk>.    Found 2-bit register for signal <rclk_count>.    Summary:	inferred  37 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred   1 Comparator(s).Unit <rece18> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors               : 2 2-bit adder                       : 1 8-bit adder                       : 1# Registers                        : 5 1-bit register                    : 1 18-bit register                   : 1 2-bit register                    : 1 8-bit register                    : 2# Latches                          : 1 1-bit latch                       : 1# Comparators                      : 1 8-bit comparator equal            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Register <f_datain_7> equivalent to <b_7> has been removedRegister <f_datain_0> equivalent to <b_0> has been removedRegister <f_datain_1> equivalent to <b_1> has been removedRegister <f_datain_2> equivalent to <b_2> has been removedRegister <f_datain_3> equivalent to <b_3> has been removedRegister <f_datain_4> equivalent to <b_4> has been removedRegister <f_datain_5> equivalent to <b_5> has been removedRegister <f_datain_6> equivalent to <b_6> has been removedOptimizing unit <rece18> ...Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rece18, actual ratio is 1.FlipFlop f_rclk has been replicated 2 time(s)=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s100etq144-6  Number of Slices:                      21  out of   1200     1%   Number of Slice Flip Flops:            32  out of   2400     1%   Number of 4 input LUTs:                19  out of   2400     0%   Number of bonded IOBs:                 29  out of    102    28%   Number of GCLKs:                        2  out of      4    50%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+f_rclk:Q                           | BUFG                   | 26    |_n0022(_n002210:O)                 | NONE(*)(led1)          | 1     |fosc60m                            | BUFGP                  | 5     |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.Timing Summary:---------------Speed Grade: -6   Minimum period: 4.845ns (Maximum Frequency: 206.398MHz)   Minimum input arrival time before clock: 6.022ns   Maximum output required time after clock: 6.613ns   Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\2222/_ngo -i -p xc2s100e-tq144-6rece18.ngc rece18.ngd Reading NGO file 'D:/2222/rece18.ngc' ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "rece18.ngd" ...Writing NGDBUILD log file "rece18.bld"...NGDBUILD done.
Started process "Map".Using target part "2s100etq144-6".Mapping design into LUTs...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors:      0Number of warnings:    1Logic Utilization:  Number of Slice Flip Flops:        13 out of  2,400    1%  Number of 4 input LUTs:            13 out of  2,400    1%Logic Distribution:    Number of occupied Slices:                          13 out of  1,200    1%    Number of Slices containing only related logic:     13 out of     13  100%    Number of Slices containing unrelated logic:         0 out of     13    0%        *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs:           20 out of  2,400    1%      Number used as logic:                        13      Number used as a route-thru:                  7   Number of bonded IOBs:            28 out of     98   28%      IOB Flip Flops:                              18      IOB Latches:                                  1   Number of GCLKs:                   2 out of      4   50%   Number of GCLKIOBs:                1 out of      4   25%Total equivalent gate count for design:  385Additional JTAG gate count for IOBs:  1,392Peak Memory Usage:  97 MBNOTES:   Related logic is defined as being logic that shares connectivity - e.g. two   LUTs are "related" if they share common inputs.  When assembling slices,   Map gives priority to combine logic that is related.  Doing so results in   the best timing performance.   Unrelated logic shares no connectivity.  Map will only begin packing   unrelated logic into a slice once 99% of the slices are occupied through   related logic packing.   Note that once logic distribution reaches the 99% level through related   logic packing, this does not mean the device is completely utilized.   Unrelated logic packing will then begin, continuing until all usable LUTs   and FFs are occupied.  Depending on your timing budget, increased levels of   unrelated logic packing may adversely affect the overall timing performance   of your design.Mapping completed.See MAP report file "rece18_map.mrp" for details.
Started process "Place & Route".Constraints file: rece18.pcf.Loading device for application Rf_Device from file '2s100e.nph' in environmentD:/Xilinx.   "rece18" is an NCD, version 3.1, device xc2s100e, package tq144, speed -6Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000Celsius)Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)Device speed data version:  "PRODUCTION 1.18 2005-01-22".Device Utilization Summary:   Number of GCLKs                     2 out of 4      50%   Number of External GCLKIOBs         1 out of 4      25%      Number of LOCed GCLKIOBs         0 out of 1       0%   Number of External IOBs            28 out of 98     28%      Number of LOCed IOBs             0 out of 28      0%   Number of SLICEs                   13 out of 1200    1%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Starting PlacerPhase 1.1Phase 1.1 (Checksum:98976f) REAL time: 6 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 6 secs Phase 3.23Phase 3.23 (Checksum:1c9c37d) REAL time: 6 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 6 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 6 secs Phase 6.8.Phase 6.8 (Checksum:99350d) REAL time: 6 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 6 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 6 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 6 secs Writing design to file rece18.ncdTotal REAL time to Placer completion: 6 secs Total CPU time to Placer completion: 0 secs Starting RouterPhase 1: 114 unrouted;       REAL time: 6 secs Phase 2: 89 unrouted;       REAL time: 6 secs Phase 3: 13 unrouted;       REAL time: 6 secs Phase 4: 0 unrouted;       REAL time: 6 secs Total REAL time to Router completion: 6 secs Total CPU time to Router completion: 0 secs Generating "PAR" statistics.**************************Generating Clock Report**************************+---------------------+--------------+------+------+------------+-------------+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+|              f_rclk |      GCLKBUF0| No   |   22 |  0.159     |  0.565      |+---------------------+--------------+------+------+------------+-------------+|       fosc60m_BUFGP |      GCLKBUF1| No   |    3 |  0.048     |  0.400      |+---------------------+--------------+------+------+------------+-------------+|              _n0022 |         Local|      |    1 |  0.000     |  2.127      |+---------------------+--------------+------+------+------------+-------------+Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 8 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  65 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file rece18.ncdPAR done!Started process "Generate Post-Place & Route Static Timing".Loading device for application Rf_Device from file '2s100e.nph' in environmentD:/Xilinx.   "rece18" is an NCD, version 3.1, device xc2s100e, package tq144, speed -6Analysis completed Sun Oct 05 09:23:54 2008--------------------------------------------------------------------------------Generating Report ...Number of warnings: 0Total time: 0 secs 

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/dd.vhd" in Library work.Architecture behavioral of Entity grst is up to date.Compiling vhdl file "D:/2222/rece18.vhd" in Library work.Entity <rece18> compiled.Entity <rece18> (Architecture <behavioral>) compiled.Compiling vhdl file "D:/2222/clk60.vhf" in Library work.Architecture behavioral of Entity clk60 is up to date.Compiling vhdl file "D:/2222/rece.vhf" in Library work.Architecture behavioral of Entity rece is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <rece> (Architecture <behavioral>).Entity <rece> analyzed. Unit <rece> generated.Analyzing Entity <grst> (Architecture <behavioral>).Entity <grst> analyzed. Unit <grst> generated.Analyzing Entity <rece18> (Architecture <behavioral>).Entity <rece18> analyzed. Unit <rece18> generated.Analyzing Entity <clk60> (Architecture <behavioral>).    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <XLXI_1> in unit <clk60>.    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <XLXI_1> in unit <clk60>.Entity <clk60> analyzed. Unit <clk60> generated.