WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_5/_n0023 is sourced by   a combinatorial pin. This is not good design practice. Use the CE pin to   control the loading of data into the flip-flop.

Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/dd.vhd" in Library work.Architecture behavioral of Entity grst is up to date.Compiling vhdl file "D:/2222/rece18.vhd" in Library work.Entity <rece18> compiled.ERROR:HDLParsers:164 - "D:/2222/rece18.vhd" Line 86. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 77076 kilobytesNumber of errors   :    1 (   0 filtered)Number of warnings :    0 (   0 filtered)Number of infos    :    0 (   0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/dd.vhd" in Library work.Architecture behavioral of Entity grst is up to date.Compiling vhdl file "D:/2222/rece18.vhd" in Library work.Entity <rece18> compiled.Entity <rece18> (Architecture <behavioral>) compiled.Compiling vhdl file "D:/2222/clk60.vhf" in Library work.Architecture behavioral of Entity clk60 is up to date.Compiling vhdl file "D:/2222/rece.vhf" in Library work.Architecture behavioral of Entity rece is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <rece> (Architecture <behavioral>).Entity <rece> analyzed. Unit <rece> generated.Analyzing Entity <grst> (Architecture <behavioral>).Entity <grst> analyzed. Unit <grst> generated.Analyzing Entity <rece18> (Architecture <behavioral>).Entity <rece18> analyzed. Unit <rece18> generated.Analyzing Entity <clk60> (Architecture <behavioral>).    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <XLXI_1> in unit <clk60>.    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <XLXI_1> in unit <clk60>.Entity <clk60> analyzed. Unit <clk60> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <clk60>.    Related source file is "D:/2222/clk60.vhf".Unit <clk60> synthesized.Synthesizing Unit <rece18>.    Related source file is "D:/2222/rece18.vhd".WARNING:Xst:737 - Found 1-bit latch for signal <led1>.    Found 18-bit adder for signal <$n0004> created at line 75.    Found 2-bit adder for signal <$n0009> created at line 110.    Found 8-bit comparator equal for signal <$n0013> created at line 81.    Found 8-bit register for signal <a>.    Found 8-bit register for signal <b>.    Found 18-bit register for signal <f_datain>.    Found 1-bit register for signal <f_rclk>.    Found 2-bit register for signal <rclk_count>.    Summary:	inferred  37 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred   1 Comparator(s).Unit <rece18> synthesized.Synthesizing Unit <grst>.    Related source file is "D:/2222/dd.vhd".    Found 1-bit register for signal <grst>.    Found 23-bit comparator less for signal <$n0001> created at line 20.    Found 23-bit up counter for signal <cnt>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <grst> synthesized.Synthesizing Unit <rece>.    Related source file is "D:/2222/rece.vhf".Unit <rece> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors               : 2 18-bit adder                      : 1 2-bit adder                       : 1# Counters                         : 1 23-bit up counter                 : 1# Registers                        : 6 1-bit register                    : 2 18-bit register                   : 1 2-bit register                    : 1 8-bit register                    : 2# Latches                          : 1 1-bit latch                       : 1# Comparators                      : 2 23-bit comparator less            : 1 8-bit comparator equal            : 1==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <rece> ...Optimizing unit <rece18> ...Optimizing unit <grst> ...Loading device for application Rf_Device from file '2s100e.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block rece, actual ratio is 4.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s100etq144-6  Number of Slices:                      65  out of   1200     5%   Number of Slice Flip Flops:            62  out of   2400     2%   Number of 4 input LUTs:                58  out of   2400     2%   Number of bonded IOBs:                 29  out of    102    28%   Number of GCLKs:                        3  out of      4    75%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+XLXI_5/f_rclk:Q                    | BUFG                   | 34    |lock                               | BUFGP                  | 1     |fosc                               | XLXI_6/XLXI_1:CLK0     | 27    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 8.288ns (Maximum Frequency: 120.656MHz)   Minimum input arrival time before clock: 6.318ns   Maximum output required time after clock: 6.613ns   Maximum combinational path delay: No path found=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd d:\2222/_ngo -uc rece.ucf -pxc2s100e-tq144-6 rece.ngc rece.ngd Reading NGO file 'D:/2222/rece.ngc' ...Applying constraints in "rece.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "rece.ngd" ...Writing NGDBUILD log file "rece.bld"...NGDBUILD done.
Started process "Map".Using target part "2s100etq144-6".Mapping design into LUTs...ERROR:MapLib:93 - Illegal LOC on IPAD symbol "lock" or BUFGP symbol "lock_BUFGP"   (output signal=lock_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site.Error found in mapping process, exiting...Errors found during the mapping phase.  Please see map report file for moredetails.  Output files will not be written.Design Summary--------------Number of errors   :   1Number of warnings :   1ERROR: MAP failedProcess "Map" did not complete.
Project Navigator Auto-Make Log File-------------------------------------



Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file "D:/2222/dd.vhd" in Library work.Architecture behavioral of Entity grst is up to date.Compiling vhdl file "D:/2222/rece18.vhd" in Library work.Entity <rece18> compiled.Entity <rece18> (Architecture <behavioral>) compiled.Compiling vhdl file "D:/2222/clk60.vhf" in Library work.Architecture behavioral of Entity clk60 is up to date.Compiling vhdl file "D:/2222/rece.vhf" in Library work.Architecture behavioral of Entity rece is up to date.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <rece> (Architecture <behavioral>).Entity <rece> analyzed. Unit <rece> generated.Analyzing Entity <grst> (Architecture <behavioral>).Entity <grst> analyzed. Unit <grst> generated.Analyzing Entity <rece18> (Architecture <behavioral>).Entity <rece18> analyzed. Unit <rece18> generated.Analyzing Entity <clk60> (Architecture <behavioral>).    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <XLXI_1> in unit <clk60>.    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <XLXI_1> in unit <clk60>.Entity <clk60> analyzed. Unit <clk60> generated.=========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <clk60>.    Related source file is "D:/2222/clk60.vhf".Unit <clk60> synthesized.Synthesizing Unit <rece18>.    Related source file is "D:/2222/rece18.vhd".WARNING:Xst:737 - Found 1-bit latch for signal <led1>.    Found 18-bit adder for signal <$n0004> created at line 75.    Found 2-bit adder for signal <$n0009> created at line 110.    Found 8-bit comparator equal for signal <$n0013> created at line 81.    Found 8-bit register for signal <a>.    Found 8-bit register for signal <b>.    Found 18-bit register for signal <f_datain>.    Found 1-bit register for signal <f_rclk>.    Found 2-bit register for signal <rclk_count>.    Summary:	inferred  37 D-type flip-flop(s).	inferred   2 Adder/Subtractor(s).	inferred   1 Comparator(s).Unit <rece18> synthesized.Synthesizing Unit <grst>.    Related source file is "D:/2222/dd.vhd".    Found 1-bit register for signal <grst>.    Found 23-bit comparator less for signal <$n0001> created at line 20.    Found 23-bit up counter for signal <cnt>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).	inferred   1 Comparator(s).Unit <grst> synthesized.Synthesizing Unit <rece>.    Related source file is "D:/2222/rece.vhf".Unit <rece> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================*                       Advanced HDL Synthesis                          *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors               : 2 18-bit adder                      : 1 2-bit adder                       : 1# Counters                         : 1 23-bit up counter                 : 1# Registers                        : 6 1-bit register                    : 2 18-bit register                   : 1 2-bit register                    : 1 8-bit register                    : 2# Latches                          : 1 1-bit latch                       : 1# Comparators                      : 2 23-bit comparator less            : 1 8-bit comparator equal            : 1==================================================================================================================================================