Release 7.1i par H.38Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.B5A6955F24534CE::  Mon Oct 13 10:57:35 2008par -w -intstyle ise -ol std -t 1 data_part_map.ncd data_part.ncd data_part.pcfConstraints file: data_part.pcf.Loading device for application Rf_Device from file '2s100e.nph' in environment
D:/Xilinx.   "data_part" is an NCD, version 3.1, device xc2s100e, package tq144, speed -6Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 85.000
Celsius)Initializing voltage to 1.700 Volts. (default - Range: 1.700 to 1.900 Volts)Device speed data version:  "PRODUCTION 1.18 2005-01-22".Device Utilization Summary:   Number of External IOBs            24 out of 98     24%      Number of LOCed IOBs             0 out of 24      0%Overall effort level (-ol):   Standard (set by user)Placer effort level (-pl):    Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl):    Standard (set by user)Starting PlacerPhase 1.1Phase 1.1 (Checksum:989697) REAL time: 0 secs Phase 2.31Phase 2.31 (Checksum:1312cfe) REAL time: 0 secs Phase 3.23Phase 3.23 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.3Phase 4.3 (Checksum:26259fc) REAL time: 0 secs Phase 5.5Phase 5.5 (Checksum:2faf07b) REAL time: 0 secs Phase 6.8Phase 6.8 (Checksum:98b29f) REAL time: 0 secs Phase 7.5Phase 7.5 (Checksum:42c1d79) REAL time: 0 secs Phase 8.18Phase 8.18 (Checksum:4c4b3f8) REAL time: 0 secs Phase 9.5Phase 9.5 (Checksum:55d4a77) REAL time: 0 secs Writing design to file data_part.ncdTotal REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Starting RouterPhase 1: 12 unrouted;       REAL time: 1 secs Phase 2: 12 unrouted;       REAL time: 1 secs Phase 3: 0 unrouted;       REAL time: 1 secs Phase 4: 0 unrouted;       REAL time: 1 secs Total REAL time to Router completion: 1 secs Total CPU time to Router completion: 0 secs Generating "PAR" statistics.INFO:Par:340 -    The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.Generating Pad Report.All signals are completely routed.Total REAL time to PAR completion: 1 secs Total CPU time to PAR completion: 0 secs Peak Memory Usage:  65 MBPlacement: Completed - No errors found.Routing: Completed - No errors found.Number of error messages: 0Number of warning messages: 0Number of info messages: 1Writing design to file data_part.ncdPAR done!