library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_part is
	port(
		datain:in std_logic_vector(11 downto 0);
		dataout1:out std_logic_vector(1 downto 0);
		dataout2:out std_logic_vector(1 downto 0);
		dataout3:out std_logic_vector(1 downto 0);
		dataout4:out std_logic_vector(1 downto 0);
		dataout5:out std_logic_vector(1 downto 0);
		dataout6:out std_logic_vector(1 downto 0)
		);
end data_part;

architecture Behavioral of data_part is
--signal   f_datain :std_logic_vector(11 downto 0);
begin
		dataout1<=datain(1 downto 0);
		dataout2<=datain(3 downto 2);
		dataout3<=datain(5 downto 4);
		dataout4<=datain(7 downto 6);
		dataout5<=datain(9 downto 8);
		dataout6<=datain(11 downto 10);
end Behavioral;