?? fifo12bit_2k.mrp
字號:
Release 7.1i Map H.38Xilinx Mapping Report File for Design 'fifo12bit_2k'Design Information------------------Command Line : D:/Xilinx/bin/nt/map.exe -ise d:\2222\2222.ise -intstyle ise -p
xc2s100e-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o fifo12bit_2k_map.ncd
fifo12bit_2k.ngd fifo12bit_2k.pcf Target Device : xc2s100eTarget Package : tq144Target Speed : -6Mapper Version : spartan2e -- $Revision: 1.26.6.3 $Mapped Date : Mon Oct 13 11:04:34 2008Design Summary--------------Number of errors: 0Number of warnings: 2Logic Utilization:Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 46 out of 98 46% Number of Block RAMs: 6 out of 10 60% Number of GCLKs: 2 out of 4 50% Number of GCLKIOBs: 2 out of 4 50%Total equivalent gate count for design: 98,304Additional JTAG gate count for IOBs: 2,304Peak Memory Usage: 97 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network XLXN_84 has no load.WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 40
more times for the following (max. 5 shown): fifowr_BUFGP, adda_9_IBUF, fiford_BUFGP, adda_4_IBUF, addb_8_IBUF To see the details of these warning messages, please use the -detail switch.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 5 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKVCC XLXI_25VCC XLXI_27GND XLXI_29GND XLXI_30GND XLXI_32Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| fiford | GCLKIOB | INPUT | LVTTL | | | | | || fifowr | GCLKIOB | INPUT | LVTTL | | | | | || adda<0> | IOB | INPUT | LVTTL | | | | | || adda<1> | IOB | INPUT | LVTTL | | | | | || adda<2> | IOB | INPUT | LVTTL | | | | | || adda<3> | IOB | INPUT | LVTTL | | | | | || adda<4> | IOB | INPUT | LVTTL | | | | | || adda<5> | IOB | INPUT | LVTTL | | | | | || adda<6> | IOB | INPUT | LVTTL | | | | | || adda<7> | IOB | INPUT | LVTTL | | | | | || adda<8> | IOB | INPUT | LVTTL | | | | | || adda<9> | IOB | INPUT | LVTTL | | | | | || adda<10> | IOB | INPUT | LVTTL | | | | | || addb<0> | IOB | INPUT | LVTTL | | | | | || addb<1> | IOB | INPUT | LVTTL | | | | | || addb<2> | IOB | INPUT | LVTTL | | | | | || addb<3> | IOB | INPUT | LVTTL | | | | | || addb<4> | IOB | INPUT | LVTTL | | | | | || addb<5> | IOB | INPUT | LVTTL | | | | | || addb<6> | IOB | INPUT | LVTTL | | | | | || addb<7> | IOB | INPUT | LVTTL | | | | | || addb<8> | IOB | INPUT | LVTTL | | | | | || addb<9> | IOB | INPUT | LVTTL | | | | | || addb<10> | IOB | INPUT | LVTTL | | | | | || datain<0> | IOB | INPUT | LVTTL | | | | | || datain<1> | IOB | INPUT | LVTTL | | | | | || datain<2> | IOB | INPUT | LVTTL | | | | | || datain<3> | IOB | INPUT | LVTTL | | | | | || datain<4> | IOB | INPUT | LVTTL | | | | | || datain<5> | IOB | INPUT | LVTTL | | | | | || datain<6> | IOB | INPUT | LVTTL | | | | | || datain<7> | IOB | INPUT | LVTTL | | | | | || datain<8> | IOB | INPUT | LVTTL | | | | | || datain<9> | IOB | INPUT | LVTTL | | | | | || datain<10> | IOB | INPUT | LVTTL | | | | | || datain<11> | IOB | INPUT | LVTTL | | | | | || dataout<0> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<1> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<2> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<3> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<4> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<5> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<6> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<7> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<8> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<9> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<10> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || dataout<11> | IOB | OUTPUT | LVTTL | 12 | SLOW | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 48Number of Equivalent Gates for Design = 98,304Number of RPM Macros = 0Number of Hard Macros = 0PCI IOBs = 0PCI LOGICs = 0CAPTUREs = 0BSCANs = 0STARTUPs = 0DLLs = 0GCLKIOBs = 2GCLKs = 2Block RAMs = 6TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 46XORs = 0CARRY_INITs = 0CARRY_SKIPs = 0CARRY_MUXes = 0Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MULT_ANDs = 0MUXF5s + MUXF6s = 04 input LUTs used as Route-Thrus = 04 input LUTs = 0Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 0Slice Flip Flops = 0Slices = 0F6 Muxes = 0F5 Muxes = 0Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 0Number of LUT signals with 1 load = 0NGM Average fanout of LUT = -1.#JNGM Maximum fanout of LUT = 0NGM Average fanin for LUT = -1.#IND?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -