/*
** LDF for adsp-BF561
** 
** There are a number of configuration options that can be specified
** either by compiler flags, or by linker flags directly. The options are:
** 
** USE_PROFILER0
** 	Enabled by -p. Link in profiling library, and write results to
** 	both stdout and mon.out.
** USE_PROFILER1
** 	Enabled by -p1. Only write profiling data to mon.out.
** USE_PROFILER2
** 	Enabled by -p2. Only write profiling data to stdout.
** USE_PROFILER
** 	Equivalent to USE_PROFILER0.
** __WORKAROUNDS_ENABLED
**    Defined by compiler when -workaround is used to direct LDF to
**    link with libraries that have been built with work-arounds
**    enabled.
** USE_FILEIO
**	   Always defined; enables the File I/O Support, which is necessary
**	   for printf() to produce any output.
** Builds for both Core A (p0.dxe) and Core B (p1.dxe)
** and a shared memory for the two common areas (sml2.sm) at
** the same time. Requires a main project/sub-project
** arrangement, where each sub-project generates a
** .dlb library to be linked against in the main
** project. The names of these .dlb files is fixed.
** They are: corea.dlb, coreb.dlb, sml2.dlb and sml3.dlb.
** 
*/

ARCHITECTURE(ADSP-BF561)

#ifndef __NO_STD_LIB
SEARCH_DIR( $ADI_DSP/Blackfin/lib )
#endif


/* Moving to primIO means that we must always include the FileIO support,
** so that printf() will work.
*/

#ifndef USE_FILEIO
#define USE_FILEIO 1
#endif	/* } */

#ifdef USE_PROFILER	/* { */
#define USE_PROFILER0
#endif	/* } */

#ifdef USE_PROFILER0	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define PROFFLAG prfflg0_532y.doj
#else
#define PROFFLAG prfflg0_532.doj
#endif	/* } */
// The profiler needs File I/O to write its results.
#define USE_FILEIO 1
#ifndef USE_PROFILER	/* { */
#define USE_PROFILER
#endif	/* } */
#endif	/* } */

#ifdef USE_PROFILER1	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define PROFFLAG prfflg1_532y.doj
#else
#define PROFFLAG prfflg1_532.doj
#endif	/* } */
#define USE_FILEIO 1
#ifndef USE_PROFILER	/* { */
#define USE_PROFILER
#endif	/* } */
#endif	/* } */

#ifdef USE_PROFILER2	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define PROFFLAG prfflg2_532y.doj
#else
#define PROFFLAG prfflg2_532.doj
#endif	/* } */
#define USE_FILEIO 1
#ifndef USE_PROFILER	/* { */
#define USE_PROFILER
#endif	/* } */
#endif	/* } */

#ifdef __WORKAROUNDS_ENABLED	/* { */
#define OMEGA idle532y.doj
#else
#define OMEGA idle532.doj
#endif	/* } */

#define MEMINIT __initsbsz532.doj,
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define LIBSMALL libsmall532y.dlb,
#else
#define LIBSMALL libsmall532.dlb,
#endif	/* } */

#ifdef M3_RESERVED	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define LIBM3 libm3res532y.dlb
#define LIBDSP libdspm3res532y.dlb
#define SFTFLT libsftflt532y.dlb
#else
#define LIBM3 libm3res532.dlb
#define LIBDSP libdspm3res532.dlb
#define SFTFLT libsftflt532.dlb
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define LIBM3 libm3free532y.dlb
#define LIBDSP libdsp532y.dlb
#define SFTFLT libsftflt532y.dlb
#else
#define LIBM3 libm3free532.dlb
#define LIBDSP libdsp532.dlb
#define SFTFLT libsftflt532.dlb
#endif	/* } */
#endif	/* } */

#ifdef IEEEFP	/* { */
#define FPLIBS SFTFLT, LIBDSP
#else
#define FPLIBS LIBDSP, SFTFLT
#endif	/* } */


#ifdef __ADI_MULTICORE
#ifdef __WORKAROUNDS_ENABLED
#define MC_LIBS libmc561y.dlb, libc532mty.dlb
#define MC_DATA mc_data561y.doj
#else
#define MC_LIBS libmc561.dlb, libc532mt.dlb
#define MC_DATA mc_data561.doj
#endif
#endif

#ifdef __ADI_MULTICORE
#ifdef __WORKAROUNDS_ENABLED	/* { */
#ifdef __ADI_LIBEH__
#define LIBS LIBSMALL MEMINIT LIBM3, libevent532mty.dlb, libx561mty.dlb, ibio532mty.dlb, libcpp532mtyx.dlb, libcpprt532mtyx.dlb, FPLIBS, libetsi532.dlb, OMEGA
#else /* __ADI_LIBEH__ */
#define LIBS LIBSMALL MEMINIT LIBM3, libevent532mty.dlb, libx561mty.dlb, libio561y.dlb, libcpp532mty.dlb, libcpprt532mty.dlb, FPLIBS, libetsi532.dlb, OMEGA
#endif /* __ADI_LIBEH__ */
#else /* __WORKAROUNDS_ENABLED */
#ifdef __ADI_LIBEH__
#define LIBS LIBSMALL MEMINIT LIBM3, libevent532mt.dlb, libx561mt.dlb, libio561.dlb, libcpp532xmt.dlb, libcpprt532xmt.dlb, FPLIBS, libetsi532.dlb, OMEGA
#else /* __ADI_LIBEH__ */
#define LIBS LIBSMALL MEMINIT LIBM3, libevent532mt.dlb, libx561mt.dlb, libio561.dlb, libcpp532mt.dlb, libcpprt532mt.dlb, FPLIBS, libetsi532.dlb, OMEGA
#endif /* } __ADI_LIBEH__ */
#endif	/* }  __WORKAROUNDS_ENABLED */

#else /* __ADI_MULTICORE */

#ifdef __WORKAROUNDS_ENABLED	/* { */
#ifdef __ADI_LIBEH__
#define LIBS LIBSMALL MEMINIT libc532y.dlb, LIBM3, libevent532y.dlb, libx561y.dlb, ibio532y.dlb, libcpp532yx.dlb, libcpprt532yx.dlb, FPLIBS, libetsi532.dlb, OMEGA
#else /* __ADI_LIBEH__ */
#define LIBS LIBSMALL MEMINIT libc532y.dlb, LIBM3, libevent532y.dlb, libx561y.dlb, libio561y.dlb, libcpp532y.dlb, libcpprt532y.dlb, FPLIBS, libetsi532.dlb, OMEGA
#endif /* __ADI_LIBEH__ */
#else /* __WORKAROUNDS_ENABLED */
#ifdef __ADI_LIBEH__
#define LIBS LIBSMALL MEMINIT libc532.dlb, LIBM3, libevent532.dlb, libx561.dlb, libio561.dlb, libcpp532x.dlb, libcpprt532x.dlb, FPLIBS, libetsi532.dlb, OMEGA
#else /* __ADI_LIBEH__ */
#define LIBS LIBSMALL MEMINIT libc532.dlb, LIBM3, libevent532.dlb, libx561.dlb, libio561.dlb, libcpp532.dlb, libcpprt532.dlb, FPLIBS, libetsi532.dlb, OMEGA
#endif /* } __ADI_LIBEH__ */
#endif	/* }  __WORKAROUNDS_ENABLED */
#endif      /* __ADI_MULTICORE */

#if defined(USE_FILEIO) || defined(USE_PROFGUIDE)
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define RTLIB librt_fileio532y.dlb
#else
#define RTLIB librt_fileio532.dlb
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define RTLIB librt532y.dlb
#else
#define RTLIB librt532.dlb
#endif	/* } */
#endif	/* } */
$LIBRARIES_CORE_A = corea.dlb, LIBS, RTLIB;
$LIBRARIES_CORE_B = coreb.dlb, LIBS, RTLIB;
#if defined(__ADI_MULTICORE)
$LIBRARIES_SML2 = MC_DATA, sml2.dlb, MC_LIBS, LIBS, RTLIB;
#else
$LIBRARIES_SML2 = sml2.dlb, LIBS, RTLIB;
#endif
$LIBRARIES_SML3 = sml3.dlb, LIBS, RTLIB;

// Libraries from the command line are included in COMMAND_LINE_OBJECTS.

#ifdef USE_PROFILER	/* { */
#ifdef USE_FILEIO	/* { */
#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT crtsfpc561y.doj, libprofile532y.dlb, PROFFLAG
#else
#define CRT crtsfpc561.doj, libprofile532.dlb, PROFFLAG
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT crtsfp561y.doj, libprofile532y.dlb, PROFFLAG
#else
#define CRT crtsfp561.doj, libprofile532.dlb, PROFFLAG
#endif	/* } */
#endif  /* __cplusplus */	/* } */
#else
#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT crtscp561y.doj, libprofile532y.dlb, PROFFLAG
#else
#define CRT crtscp561.doj, libprofile532.dlb, PROFFLAG
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT crtsp561y.doj, libprofile532y.dlb, PROFFLAG
#else
#define CRT crtsp561.doj, libprofile532.dlb, PROFFLAG
#endif	/* } */
#endif  /* __cplusplus */	/* } */
#endif  /* USE_FILEIO */	/* } */
#else
#ifdef USE_FILEIO	/* { */
#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT  crtsfc561y.doj
#else
#define CRT  crtsfc561.doj
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT  crtsf561y.doj
#else
#define CRT  crtsf561.doj
#endif	/* } */
#endif /* __cplusplus */	/* } */
#else
#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT  crtsc561y.doj
#else
#define CRT  crtsc561.doj
#endif	/* } */
#else
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define CRT	crts561y.doj
#else
#define CRT	crts561.doj
#endif	/* } */
#endif /* __cplusplus */	/* } */
#endif  /* USE_FILEIO */	/* } */
#endif  /* USE_PROFILER */	/* } */

#ifdef __cplusplus	/* { */
#ifdef __WORKAROUNDS_ENABLED	/* { */
#define ENDCRT , crtn561y.doj
#else
#define ENDCRT , crtn561.doj
#endif	/* } */
#else
#define ENDCRT
#endif	/* } */
$OBJECTS_CORE_A = CRT, $COMMAND_LINE_OBJECTS ,cplbtab561a.doj ENDCRT;
$OBJECTS_CORE_B = CRT, $COMMAND_LINE_OBJECTS ,cplbtab561b.doj ENDCRT;
$OBJECTS = $COMMAND_LINE_OBJECTS;


MEMORY
	/* L2 SRAM - 128K. */{
/* Shared area for file I/O Control variable */
/*        - FEB1FCF0 - FEB1FBFF */
MEM_SHARED_TESTSET   {
     TYPE(RAM) WIDTH(8)
     START(0xFEB1FBF0) END(0xFEB1FBFF)
}
 /* FEB1FC00 - FEB1FFFF : Reseved in boot Phase for 2nd stage boot loader */
MEM_L2_SRAM     {
	TYPE(RAM) WIDTH(8)
	START(0xFEB13000) END(0xFEB1FBEF)
}
MEM_L2_SRAM_BSZ     {	
	TYPE(RAM) WIDTH(8)
	START(0xFEB00000) END(0xFEB12FFF)
}
MEM_ASYNC3     {	/* Async Bank 3 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20300000) END(0x203FFFFF)
}
MEM_ASYNC2     {	/* Async Bank 2 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20200000) END(0x202FFFFF)
}
MEM_ASYNC1     {	/* Async Bank 1 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20100000) END(0x201FFFFF)
}
MEM_ASYNC0     {	/* Async Bank 0 - 1MB */
	TYPE(RAM) WIDTH(8)
	START(0x20000000) END(0x200FFFFF)
}

/* Claim some of SDRAM Bank 0 for heap */
/* since it needs a separate section */
	/* SDRAM Bank 0 - 16MB-128M */
MEM_SDRAM0     {
	TYPE(RAM) WIDTH(8)
	START(0x00004000) END(0x07FFFFFF)
}
/*  Declare heap for both cores. If __ADI_MULTICORE is defined,
 ** we use a shared heap. If not, each core has it's own space.
 */
#if defined(__ADI_MULTICORE)
/*  Heap is to be shared between both cores. It must reside in a
 ** Shared memory location, and can only be accessed using the
 ** re-entrant safe libraries.
 */
MEM_SDRAM0_HEAP     {	/* Claim some for ext heap - 16K */
	TYPE(RAM) WIDTH(8)
	START(0x00002000) END(0x00003FFF)
}
#else
/*  A separate heapspace is allocated for each core.
 ** The heaps should only be accessed by the correct core.
 ** Re-entrant safe libraries do not need to be used.
 */
MEM_SDRAM0_HEAP_A     {	/* Claim some for ext heap - 8K */
	TYPE(RAM) WIDTH(8)
	START(0x00000004) END(0x00001FFF)
}
MEM_SDRAM0_HEAP_B     {	/* Claim some for ext heap - 8K */
	TYPE(RAM) WIDTH(8)
	START(0x00002000) END(0x00003FFF)
}
#endif
}
SHARED_MEMORY
{
	OUTPUT($COMMAND_LINE_OUTPUT_DIRECTORY/sml2.sm)
   SECTIONS {
        l2_sram
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(l2_sram) $LIBRARIES_SML2(l2_sram))
            INPUT_SECTIONS( $LIBRARIES_SML2(noncache_code))
            INPUT_SECTIONS( $LIBRARIES_SML2(program))
            INPUT_SECTIONS( $LIBRARIES_SML2(data1))
            INPUT_SECTIONS( $LIBRARIES_SML2(constdata))
        } >MEM_L2_SRAM

        l2_sram_voldata
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(voldata) $LIBRARIES_SML2(voldata))
        } >MEM_L2_SRAM
#ifdef __ADI_MULTICORE
        mc_data
        {
             INPUT_SECTION_ALIGN(4)
             INPUT_SECTIONS( $OBJECTS(mc_data) $LIBRARIES_SML2(mc_data))
        } >MEM_L2_SRAM
#endif

        l2_bsz ZERO_INIT
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $LIBRARIES_SML2(bsz))
        } >MEM_L2_SRAM

        primio_atomic_lock
        {
            // Holds control variable used to ensure atomic file I/O
            // Must be in shared memory and NOT cached.
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $LIBRARIES_SML2(primio_atomic_lock))
        } >MEM_SHARED_TESTSET

        sdram0
        {
            INPUT_SECTION_ALIGN(4)
            INPUT_SECTIONS( $OBJECTS(sdram0) $LIBRARIES_SML3(sdram0))
            INPUT_SECTIONS( $LIBRARIES_SML3(noncache_code))
            INPUT_SECTIONS( $LIBRARIES_SML3(program))
            INPUT_SECTIONS( $LIBRARIES_SML3(data1))
            INPUT_SECTIONS( $LIBRARIES_SML3(constdata))
        } >MEM_SDRAM0

        sdram0_voldata
        {
            INPUT_SECTION_ALIGN(4)