/************************************************************************
 *
 * cdefBF561.h
 *
 * (c) Copyright 2001-2004 Analog Devices, Inc.  All rights reserved.
 *
 ************************************************************************/

/* C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561 */

#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H

#if !defined(__ADSPBF561__)
#warning cdefBF561.h should only be included for BF561 chip.
#endif
// include all Core registers and bit definitions
#include <defBF561.h>
#include <cdef_LPBlackfin.h>

//**********************************************************************************
// System MMR Register Map
//**********************************************************************************

//// Clock and System Control (0xFFC00000 - 0xFFC000FF)
#define pPLL_CTL (volatile unsigned short *)PLL_CTL
#define pPLL_DIV (volatile unsigned short *)PLL_DIV
#define pVR_CTL (volatile unsigned short *)VR_CTL
#define pPLL_STAT (volatile unsigned short *)PLL_STAT
#define pPLL_LOCKCNT (volatile unsigned short *)PLL_LOCKCNT

// System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF)
#define pSICA_SWRST (volatile unsigned short *)SICA_SWRST
#define pSICA_SYSCR (volatile unsigned short *)SICA_SYSCR
#define pSICA_RVECT (volatile unsigned short *)SICA_RVECT
#define pSICA_IMASK (volatile unsigned long *)SICA_IMASK
#define pSICA_IMASK0 (volatile unsigned long *)SICA_IMASK0
#define pSICA_IMASK1 (volatile unsigned long *)SICA_IMASK1
#define pSICA_IAR0 (volatile unsigned long *)SICA_IAR0
#define pSICA_IAR1 (volatile unsigned long *)SICA_IAR1
#define pSICA_IAR2 (volatile unsigned long *)SICA_IAR2
#define pSICA_IAR3 (volatile unsigned long *)SICA_IAR3
#define pSICA_IAR4 (volatile unsigned long *)SICA_IAR4
#define pSICA_IAR5 (volatile unsigned long *)SICA_IAR5
#define pSICA_IAR6 (volatile unsigned long *)SICA_IAR6
#define pSICA_IAR7 (volatile unsigned long *)SICA_IAR7
#define pSICA_ISR0 (volatile unsigned long *)SICA_ISR0
#define pSICA_ISR1 (volatile unsigned long *)SICA_ISR1
#define pSICA_IWR0 (volatile unsigned long *)SICA_IWR0
#define pSICA_IWR1 (volatile unsigned long *)SICA_IWR1

// System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF)
#define pSICB_SWRST (volatile unsigned short *)SICB_SWRST
#define pSICB_SYSCR (volatile unsigned short *)SICB_SYSCR
#define pSICB_RVECT (volatile unsigned short *)SICB_RVECT
#define pSICB_IMASK0 (volatile unsigned long *)SICB_IMASK0
#define pSICB_IMASK1 (volatile unsigned long *)SICB_IMASK1
#define pSICB_IAR0 (volatile unsigned long *)SICB_IAR0
#define pSICB_IAR1 (volatile unsigned long *)SICB_IAR1
#define pSICB_IAR2 (volatile unsigned long *)SICB_IAR2
#define pSICB_IAR3 (volatile unsigned long *)SICB_IAR3
#define pSICB_IAR4 (volatile unsigned long *)SICB_IAR4
#define pSICB_IAR5 (volatile unsigned long *)SICB_IAR5
#define pSICB_IAR6 (volatile unsigned long *)SICB_IAR6
#define pSICB_IAR7 (volatile unsigned long *)SICB_IAR7
#define pSICB_ISR0 (volatile unsigned long *)SICB_ISR0
#define pSICB_ISR1 (volatile unsigned long *)SICB_ISR1
#define pSICB_IWR0 (volatile unsigned long *)SICB_IWR0
#define pSICB_IWR1 (volatile unsigned long *)SICB_IWR1
// Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF)
#define pWDOGA_CTL (volatile unsigned short *)WDOGA_CTL
#define pWDOGA_CNT (volatile unsigned long *)WDOGA_CNT
#define pWDOGA_STAT (volatile unsigned long *)WDOGA_STAT

// Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF)
#define pWDOGB_CTL (volatile unsigned short *)WDOGB_CTL
#define pWDOGB_CNT (volatile unsigned long *)WDOGB_CNT
#define pWDOGB_STAT (volatile unsigned long *)WDOGB_STAT

// UART Controller (0xFFC00400 - 0xFFC004FF)
#define pUART_THR (volatile unsigned short *)UART_THR
#define pUART_RBR (volatile unsigned short *)UART_RBR
#define pUART_DLL (volatile unsigned short *)UART_DLL
#define pUART_IER (volatile unsigned short *)UART_IER
#define pUART_DLH (volatile unsigned short *)UART_DLH
#define pUART_IIR (volatile unsigned short *)UART_IIR
#define pUART_LCR (volatile unsigned short *)UART_LCR
#define pUART_MCR (volatile unsigned short *)UART_MCR
#define pUART_LSR (volatile unsigned short *)UART_LSR
#define pUART_MSR (volatile unsigned short *)UART_MSR
#define pUART_SCR (volatile unsigned short *)UART_SCR
#define pUART_GCTL (volatile unsigned short *)UART_GCTL

// SPI Controller (0xFFC00500 - 0xFFC005FF)
#define pSPI_CTL (volatile unsigned short *)SPI_CTL
#define pSPI_FLG (volatile unsigned short *)SPI_FLG
#define pSPI_STAT (volatile unsigned short *)SPI_STAT
#define pSPI_TDBR (volatile unsigned short *)SPI_TDBR
#define pSPI_RDBR (volatile unsigned short *)SPI_RDBR
#define pSPI_BAUD (volatile unsigned short *)SPI_BAUD
#define pSPI_SHADOW (volatile unsigned short *)SPI_SHADOW

// Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF)
#define pTIMER0_CONFIG (volatile unsigned short *)TIMER0_CONFIG
#define pTIMER0_COUNTER (volatile unsigned long *)TIMER0_COUNTER
#define pTIMER0_PERIOD (volatile unsigned long *)TIMER0_PERIOD
#define pTIMER0_WIDTH (volatile unsigned long *)TIMER0_WIDTH
#define pTIMER1_CONFIG (volatile unsigned short *)TIMER1_CONFIG
#define pTIMER1_COUNTER (volatile unsigned long *)TIMER1_COUNTER
#define pTIMER1_PERIOD (volatile unsigned long *)TIMER1_PERIOD
#define pTIMER1_WIDTH (volatile unsigned long *)TIMER1_WIDTH
#define pTIMER2_CONFIG (volatile unsigned short *)TIMER2_CONFIG
#define pTIMER2_COUNTER (volatile unsigned long *)TIMER2_COUNTER
#define pTIMER2_PERIOD (volatile unsigned long *)TIMER2_PERIOD
#define pTIMER2_WIDTH (volatile unsigned long *)TIMER2_WIDTH
#define pTIMER3_CONFIG (volatile unsigned short *)TIMER3_CONFIG
#define pTIMER3_COUNTER (volatile unsigned long *)TIMER3_COUNTER
#define pTIMER3_PERIOD (volatile unsigned long *)TIMER3_PERIOD
#define pTIMER3_WIDTH (volatile unsigned long *)TIMER3_WIDTH
#define pTIMER4_CONFIG (volatile unsigned short *)TIMER4_CONFIG
#define pTIMER4_COUNTER (volatile unsigned long *)TIMER4_COUNTER
#define pTIMER4_PERIOD (volatile unsigned long *)TIMER4_PERIOD
#define pTIMER4_WIDTH (volatile unsigned long *)TIMER4_WIDTH
#define pTIMER5_CONFIG (volatile unsigned short *)TIMER5_CONFIG
#define pTIMER5_COUNTER (volatile unsigned long *)TIMER5_COUNTER
#define pTIMER5_PERIOD (volatile unsigned long *)TIMER5_PERIOD
#define pTIMER5_WIDTH (volatile unsigned long *)TIMER5_WIDTH
#define pTIMER6_CONFIG (volatile unsigned short *)TIMER6_CONFIG
#define pTIMER6_COUNTER (volatile unsigned long *)TIMER6_COUNTER
#define pTIMER6_PERIOD (volatile unsigned long *)TIMER6_PERIOD
#define pTIMER6_WIDTH (volatile unsigned long *)TIMER6_WIDTH
#define pTIMER7_CONFIG (volatile unsigned short *)TIMER7_CONFIG
#define pTIMER7_COUNTER (volatile unsigned long *)TIMER7_COUNTER
#define pTIMER7_PERIOD (volatile unsigned long *)TIMER7_PERIOD
#define pTIMER7_WIDTH (volatile unsigned long *)TIMER7_WIDTH

// Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF)
#define pTMRS8_ENABLE (volatile unsigned short *)TMRS8_ENABLE
#define pTMRS8_DISABLE (volatile unsigned short *)TMRS8_DISABLE
#define pTMRS8_STATUS (volatile unsigned long *)TMRS8_STATUS
#define pTIMER8_CONFIG (volatile unsigned short *)TIMER8_CONFIG
#define pTIMER8_COUNTER (volatile unsigned long *)TIMER8_COUNTER
#define pTIMER8_PERIOD (volatile unsigned long *)TIMER8_PERIOD
#define pTIMER8_WIDTH (volatile unsigned long *)TIMER8_WIDTH
#define pTIMER9_CONFIG (volatile unsigned short *)TIMER9_CONFIG
#define pTIMER9_COUNTER (volatile unsigned long *)TIMER9_COUNTER
#define pTIMER9_PERIOD (volatile unsigned long *)TIMER9_PERIOD
#define pTIMER9_WIDTH (volatile unsigned long *)TIMER9_WIDTH
#define pTIMER10_CONFIG (volatile unsigned short *)TIMER10_CONFIG
#define pTIMER10_COUNTER (volatile unsigned long *)TIMER10_COUNTER
#define pTIMER10_PERIOD (volatile unsigned long *)TIMER10_PERIOD
#define pTIMER10_WIDTH (volatile unsigned long *)TIMER10_WIDTH
#define pTIMER11_CONFIG (volatile unsigned short *)TIMER11_CONFIG
#define pTIMER11_COUNTER (volatile unsigned long *)TIMER11_COUNTER
#define pTIMER11_PERIOD (volatile unsigned long *)TIMER11_PERIOD
#define pTIMER11_WIDTH (volatile unsigned long *)TIMER11_WIDTH
#define pTMRS4_ENABLE (volatile unsigned short *)TMRS4_ENABLE
#define pTMRS4_DISABLE (volatile unsigned short *)TMRS4_DISABLE
#define pTMRS4_STATUS (volatile unsigned long *)TMRS4_STATUS

// Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF)
#define pFIO0_FLAG_D (volatile unsigned short *)FIO0_FLAG_D
#define pFIO0_FLAG_C (volatile unsigned short *)FIO0_FLAG_C
#define pFIO0_FLAG_S (volatile unsigned short *)FIO0_FLAG_S
#define pFIO0_FLAG_T (volatile unsigned short *)FIO0_FLAG_T
#define pFIO0_MASKA_D (volatile unsigned short *)FIO0_MASKA_D
#define pFIO0_MASKA_C (volatile unsigned short *)FIO0_MASKA_C
#define pFIO0_MASKA_S (volatile unsigned short *)FIO0_MASKA_S
#define pFIO0_MASKA_T (volatile unsigned short *)FIO0_MASKA_T
#define pFIO0_MASKB_D (volatile unsigned short *)FIO0_MASKB_D
#define pFIO0_MASKB_C (volatile unsigned short *)FIO0_MASKB_C
#define pFIO0_MASKB_S (volatile unsigned short *)FIO0_MASKB_S
#define pFIO0_MASKB_T (volatile unsigned short *)FIO0_MASKB_T
#define pFIO0_DIR (volatile unsigned short *)FIO0_DIR
#define pFIO0_POLAR (volatile unsigned short *)FIO0_POLAR
#define pFIO0_EDGE (volatile unsigned short *)FIO0_EDGE
#define pFIO0_BOTH (volatile unsigned short *)FIO0_BOTH
#define pFIO0_INEN (volatile unsigned short *)FIO0_INEN
// Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF)
#define pFIO1_FLAG_D (volatile unsigned short *)FIO1_FLAG_D
#define pFIO1_FLAG_C (volatile unsigned short *)FIO1_FLAG_C
#define pFIO1_FLAG_S (volatile unsigned short *)FIO1_FLAG_S
#define pFIO1_FLAG_T (volatile unsigned short *)FIO1_FLAG_T
#define pFIO1_MASKA_D (volatile unsigned short *)FIO1_MASKA_D
#define pFIO1_MASKA_C (volatile unsigned short *)FIO1_MASKA_C
#define pFIO1_MASKA_S (volatile unsigned short *)FIO1_MASKA_S
#define pFIO1_MASKA_T (volatile unsigned short *)FIO1_MASKA_T
#define pFIO1_MASKB_D (volatile unsigned short *)FIO1_MASKB_D
#define pFIO1_MASKB_C (volatile unsigned short *)FIO1_MASKB_C
#define pFIO1_MASKB_S (volatile unsigned short *)FIO1_MASKB_S
#define pFIO1_MASKB_T (volatile unsigned short *)FIO1_MASKB_T
#define pFIO1_DIR (volatile unsigned short *)FIO1_DIR