;   Copyright(C) Renesas Technology Corp. 2002-2005. All rights reserved.
;
;   header file for ITS-DS7 Ver.1.0.0
;
;   FILE      : ITS_DS7.inc
;   CREATED   : 2002.04.25
;   MODIFIED  : 2005.06.09
;   AUTHOR    : Renesas Technology Corp.
;   HARDWARE  : RENESAS ITS-DS7
;   HISTORY   : 
;               2003.06.20
;               - Created release code.
;                 (based on RENESAS ITS-DS4 Source Kit Ver.1.2.0 for WCE4.2)
;               2005.06.09
;               - Modified memory mapping for Multiple XIP.
;

;// define for ITS_DS7_SETTING

ITS_DS7_COREONLY		.equ		1
ITS_DS7_COREFUNCTION	.equ		2

;######### P=50MHz ###########################################
USEC_TO_CLOCK_LOW       .equ	h'80000000
USEC_TO_CLOCK_HIGH      .equ	h'0000000C
CLOCK_TO_USEC_LOW       .equ	h'147AE148
CLOCK_TO_USEC_HIGH      .equ	h'00000000


; Area address offset definitions
AREA_0          		.equ	h'00000000
AREA_1          		.equ	h'04000000
AREA_2          		.equ	h'08000000
AREA_3          		.equ	h'0C000000
AREA_4          		.equ	h'10000000
AREA_5          		.equ	h'14000000
AREA_6          		.equ	h'18000000
AREA_7          		.equ	h'FC000000

CACHED_BASE     		.equ	h'80000000
UNCACHED_BASE   		.equ	h'A0000000


DRAM_BASE               .equ	(AREA_3 + CACHED_BASE)
UNCACHED_DRAM_BASE      .equ	(AREA_3 + UNCACHED_BASE)
BACKUP_DRAM_BASE        .equ	(AREA_2 + CACHED_BASE)
UNCACHED_BACKUP_DRAM_BASE	.equ	 (AREA_2 + UNCACHED_BASE)

DRV_GLOBAL_OFFSET       .equ	h'0012F000
DRV_GLOBAL_BASE         .equ	(DRV_GLOBAL_OFFSET + UNCACHED_BACKUP_DRAM_BASE)

PF_ETHER_OFFSET         .equ	h'00180000
PF_ETHER_BASE           .equ	(AREA_6 + UNCACHED_BASE + PF_ETHER_OFFSET)

SYSTEM_FPGA_OFFSET		.equ	h'00100000
SYSTEM_FPGA_BASE		.equ	(AREA_6 + UNCACHED_BASE + SYSTEM_FPGA_OFFSET)

SF_SRSTR_OFFSET			.equ	h'00000000
SF_SNMIR_OFFSET			.equ	h'00000010
SF_IRQSR_OFFSET			.equ	h'00000020
SF_IRQMR_OFFSET			.equ	h'00000030
SF_MAPSWR_OFFSET		.equ	h'00000040
SF_FPVERR_OFFSET		.equ	h'00000050
SF_FPDATER_OFFSET		.equ	h'00000060
SF_DIPSWMR_OFFSET		.equ	h'00001000
SF_FPODR_OFFSET			.equ	h'00001010
SF_ATAESR_OFFSET		.equ	h'00001020
SF_LED_OFFSET			.equ	h'00002000

SF_SRSTR				.equ	(SYSTEM_FPGA_BASE + SF_SRSTR_OFFSET )
SF_SNMIR				.equ	(SYSTEM_FPGA_BASE + SF_SNMIR_OFFSET )
SF_IRQSR				.equ	(SYSTEM_FPGA_BASE + SF_IRQSR_OFFSET )
SF_IRQMR				.equ	(SYSTEM_FPGA_BASE + SF_IRQMR_OFFSET )
SF_MAPSWR				.equ	(SYSTEM_FPGA_BASE + SF_MAPSWR_OFFSET )
SF_FPVERR				.equ	(SYSTEM_FPGA_BASE + SF_FPVERR_OFFSET )
SF_FPDATER				.equ	(SYSTEM_FPGA_BASE + SF_FPDATER_OFFSET )
SF_DIPSWMR				.equ	(SYSTEM_FPGA_BASE + SF_DIPSWMR_OFFSET )
SF_FPODR				.equ	(SYSTEM_FPGA_BASE + SF_FPODR_OFFSET )
SF_ATAESR				.equ	(SYSTEM_FPGA_BASE + SF_ATAESR_OFFSET)
SF_LED					.equ	(SYSTEM_FPGA_BASE + SF_LED_OFFSET)
LED_ALPHA				.equ	(SF_LED + h'70 ) ;// Top of 8 registers
; LED_ALPHA				.equ	h'B8102070
LED_ALPHA_STRIDE        .equ    2


;	ASCII code for LED ALPHA
;
;		2	3	4	5	6	7	
;	0	SP	0	@	P		p	
;	1	!	1	A	Q	a	q	
;	2	"	2	B	R	b	r	
;	3	#	3	C	S	c	s	
;	4	$	4	D	T	d	t	
;	5	%	5	E	U	e	u	
;	6	&	6	F	V	f	v	
;	7	'	7	G	W	g	w	
;	8	(	8	H	X	h	x	
;	9	)	9	I	Y	i	y	
;	A	*	:	J	Z	j	z	
;	B	+	;	K	[	k	{	
;	C	,	<	L	\	l	|	
;	D	-	=	M	]	m	}	
;	E	.	>	N	^	n	~	
;	F	/	?	O	-	o	DEL	


; Address definition related to SH7751 PCIC
;PCI_MEM_BASE    		.equ	h'FD000000
;PCI_REG_BASE    		.equ	h'FE200000
;PCI_IO_BASE     		.equ	h'FE240000
;PCI_LB_MAP_MEM  		.equ	h'01000000
;PCI_LB_MAP_IO   		.equ	h'00000000


; Interrupt priorities for INTC IPRs.
;INTC_IPRA_TMU0_INT  	.equ	h'1000
;INTC_IPRA_TMU1_INT  	.equ	h'0E00
;INTC_IPRA_TMU2_INT  	.equ	h'0010
;INTC_IPRA_RTC_INT   	.equ	h'000F
;INTC_IPRB_WDT_INT   	.equ	h'0000
;INTC_IPRB_REF_INT   	.equ	h'0000
;INTC_IPRB_SCI_INT   	.equ	h'0000
;INTC_IPRC_DMAC_INT  	.equ	h'0A00
;INTC_IPRC_SCIF_INT  	.equ	h'00B0
;INTC_IPRC_JTAG_INT  	.equ	h'0000

; Reschedule period in ms, moved from TIMER.H
RESCHED_PERIOD      	.equ	1 ; 1ms